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[Qemu-devel] [PATCH v2 00/15] target-sparc improvements
From: |
Richard Henderson |
Subject: |
[Qemu-devel] [PATCH v2 00/15] target-sparc improvements |
Date: |
Tue, 18 Oct 2016 19:34:15 -0700 |
The two main goals in this patch set are:
* Make use of the new MO_ALIGN_* flags, to allow less use of
check_align, and support partially misaligned fp memory ops.
* More cleanups for ASIs, in the end using the new atomic ops.
The final two patches require the "cmpxchg atomic" v6 patch set.
Otherwise this patch set should apply to master. The full tree
is at
git://github.com/rth7680/qemu.git tgt-sparc-6
Changes since v1:
* The "Remove asi helper code handled inline" patch retains the
code within ldda to handle asis that must be handled out of line.
This fixes the FreeBSD 10.3 boot problem. While the UA2007 spec
(and thus sun4v?) doesn't allow for such, it would seem that US2
hardware does.
* Dropped the "Optimize writeback of cpu_cond" patch.
This fixes the debian 7.8 install. Not sure exactly what's wrong
with it yet, but let's just drop it for now.
r~
Richard Henderson (15):
target-sparc: Use overalignment flags for twinx and block asis
target-sparc: Introduce cpu_raise_exception_ra
target-sparc: Add MMU_PHYS_IDX
target-sparc: Use MMU_PHYS_IDX for bypass asis
target-sparc: Handle more twinx asis
target-sparc: Implement swap_asi inline
target-sparc: Implement ldstub_asi inline
target-sparc: Implement cas_asi/casx_asi inline
target-sparc: Implement BCOPY/BFILL inline
target-sparc: Remove asi helper code handled inline
target-sparc: Implement ldqf and stqf inline
target-sparc: Allow 4-byte alignment on fp mem ops
target-sparc: Remove MMU_MODE*_SUFFIX
target-sparc: Use tcg_gen_atomic_xchg_tl
target-sparc: Use tcg_gen_atomic_cmpxchg_tl
target-sparc/cpu.h | 34 +-
target-sparc/helper.c | 52 ++-
target-sparc/helper.h | 7 -
target-sparc/ldst_helper.c | 998 ++++++++-------------------------------------
target-sparc/mmu_helper.c | 47 ++-
target-sparc/translate.c | 434 +++++++++++++-------
target-sparc/win_helper.c | 37 +-
7 files changed, 531 insertions(+), 1078 deletions(-)
--
2.7.4
- [Qemu-devel] [PATCH v2 00/15] target-sparc improvements,
Richard Henderson <=
- [Qemu-devel] [PATCH v2 01/15] target-sparc: Use overalignment flags for twinx and block asis, Richard Henderson, 2016/10/18
- [Qemu-devel] [PATCH v2 03/15] target-sparc: Add MMU_PHYS_IDX, Richard Henderson, 2016/10/18
- [Qemu-devel] [PATCH v2 05/15] target-sparc: Handle more twinx asis, Richard Henderson, 2016/10/18
- [Qemu-devel] [PATCH v2 02/15] target-sparc: Introduce cpu_raise_exception_ra, Richard Henderson, 2016/10/18
- [Qemu-devel] [PATCH v2 04/15] target-sparc: Use MMU_PHYS_IDX for bypass asis, Richard Henderson, 2016/10/18
- [Qemu-devel] [PATCH v2 06/15] target-sparc: Implement swap_asi inline, Richard Henderson, 2016/10/18
- [Qemu-devel] [PATCH v2 07/15] target-sparc: Implement ldstub_asi inline, Richard Henderson, 2016/10/18
- [Qemu-devel] [PATCH v2 09/15] target-sparc: Implement BCOPY/BFILL inline, Richard Henderson, 2016/10/18
- [Qemu-devel] [PATCH v2 08/15] target-sparc: Implement cas_asi/casx_asi inline, Richard Henderson, 2016/10/18
- [Qemu-devel] [PATCH v2 12/15] target-sparc: Allow 4-byte alignment on fp mem ops, Richard Henderson, 2016/10/18