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[Qemu-devel] [PULL 03/32] translate-all.c: Compute L1 page table propert
From: |
Peter Maydell |
Subject: |
[Qemu-devel] [PULL 03/32] translate-all.c: Compute L1 page table properties at runtime |
Date: |
Mon, 24 Oct 2016 18:24:59 +0100 |
From: Vijaya Kumar K <address@hidden>
Remove L1 page mapping table properties computing
statically using macros which is dependent on
TARGET_PAGE_BITS. Drop macros V_L1_SIZE, V_L1_SHIFT,
V_L1_BITS macros and replace with variables which are
computed at early stage of VM boot.
Removing dependency can help to make TARGET_PAGE_BITS
dynamic.
Signed-off-by: Vijaya Kumar K <address@hidden>
Message-id: address@hidden
[PMM:
assert(v_l1_shift % V_L2_BITS == 0)
cache v_l2_levels
initialize from page_init() rather than vl.c
minor code style fixes
put v_l1_size into a local where used as a loop limit]
Reviewed-by: Richard Henderson <address@hidden>
Signed-off-by: Peter Maydell <address@hidden>
---
translate-all.c | 71 +++++++++++++++++++++++++++++++++++++--------------------
1 file changed, 46 insertions(+), 25 deletions(-)
diff --git a/translate-all.c b/translate-all.c
index 8ca393c9d..86b45a1 100644
--- a/translate-all.c
+++ b/translate-all.c
@@ -97,25 +97,24 @@ typedef struct PageDesc {
#define V_L2_BITS 10
#define V_L2_SIZE (1 << V_L2_BITS)
-/* The bits remaining after N lower levels of page tables. */
-#define V_L1_BITS_REM \
- ((L1_MAP_ADDR_SPACE_BITS - TARGET_PAGE_BITS) % V_L2_BITS)
-
-#if V_L1_BITS_REM < 4
-#define V_L1_BITS (V_L1_BITS_REM + V_L2_BITS)
-#else
-#define V_L1_BITS V_L1_BITS_REM
-#endif
-
-#define V_L1_SIZE ((target_ulong)1 << V_L1_BITS)
-
-#define V_L1_SHIFT (L1_MAP_ADDR_SPACE_BITS - TARGET_PAGE_BITS - V_L1_BITS)
-
uintptr_t qemu_host_page_size;
intptr_t qemu_host_page_mask;
-/* The bottom level has pointers to PageDesc */
-static void *l1_map[V_L1_SIZE];
+/*
+ * L1 Mapping properties
+ */
+static int v_l1_size;
+static int v_l1_shift;
+static int v_l2_levels;
+
+/* The bottom level has pointers to PageDesc, and is indexed by
+ * anything from 4 to (V_L2_BITS + 3) bits, depending on target page size.
+ */
+#define V_L1_MIN_BITS 4
+#define V_L1_MAX_BITS (V_L2_BITS + 3)
+#define V_L1_MAX_SIZE (1 << V_L1_MAX_BITS)
+
+static void *l1_map[V_L1_MAX_SIZE];
/* code generation context */
TCGContext tcg_ctx;
@@ -125,6 +124,26 @@ TCGContext tcg_ctx;
__thread int have_tb_lock;
#endif
+static void page_table_config_init(void)
+{
+ uint32_t v_l1_bits;
+
+ assert(TARGET_PAGE_BITS);
+ /* The bits remaining after N lower levels of page tables. */
+ v_l1_bits = (L1_MAP_ADDR_SPACE_BITS - TARGET_PAGE_BITS) % V_L2_BITS;
+ if (v_l1_bits < V_L1_MIN_BITS) {
+ v_l1_bits += V_L2_BITS;
+ }
+
+ v_l1_size = 1 << v_l1_bits;
+ v_l1_shift = L1_MAP_ADDR_SPACE_BITS - TARGET_PAGE_BITS - v_l1_bits;
+ v_l2_levels = v_l1_shift / V_L2_BITS - 1;
+
+ assert(v_l1_bits <= V_L1_MAX_BITS);
+ assert(v_l1_shift % V_L2_BITS == 0);
+ assert(v_l2_levels >= 0);
+}
+
void tb_lock(void)
{
#ifdef CONFIG_USER_ONLY
@@ -332,6 +351,8 @@ void page_size_init(void)
static void page_init(void)
{
page_size_init();
+ page_table_config_init();
+
#if defined(CONFIG_BSD) && defined(CONFIG_USER_ONLY)
{
#ifdef HAVE_KINFO_GETVMMAP
@@ -408,10 +429,10 @@ static PageDesc *page_find_alloc(tb_page_addr_t index,
int alloc)
int i;
/* Level 1. Always allocated. */
- lp = l1_map + ((index >> V_L1_SHIFT) & (V_L1_SIZE - 1));
+ lp = l1_map + ((index >> v_l1_shift) & (v_l1_size - 1));
/* Level 2..N-1. */
- for (i = V_L1_SHIFT / V_L2_BITS - 1; i > 0; i--) {
+ for (i = v_l2_levels; i > 0; i--) {
void **p = atomic_rcu_read(lp);
if (p == NULL) {
@@ -826,10 +847,10 @@ static void page_flush_tb_1(int level, void **lp)
static void page_flush_tb(void)
{
- int i;
+ int i, l1_sz = v_l1_size;
- for (i = 0; i < V_L1_SIZE; i++) {
- page_flush_tb_1(V_L1_SHIFT / V_L2_BITS - 1, l1_map + i);
+ for (i = 0; i < l1_sz; i++) {
+ page_flush_tb_1(v_l2_levels, l1_map + i);
}
}
@@ -1883,16 +1904,16 @@ static int walk_memory_regions_1(struct
walk_memory_regions_data *data,
int walk_memory_regions(void *priv, walk_memory_regions_fn fn)
{
struct walk_memory_regions_data data;
- uintptr_t i;
+ uintptr_t i, l1_sz = v_l1_size;
data.fn = fn;
data.priv = priv;
data.start = -1u;
data.prot = 0;
- for (i = 0; i < V_L1_SIZE; i++) {
- int rc = walk_memory_regions_1(&data, (target_ulong)i << (V_L1_SHIFT +
TARGET_PAGE_BITS),
- V_L1_SHIFT / V_L2_BITS - 1, l1_map + i);
+ for (i = 0; i < l1_sz; i++) {
+ target_ulong base = i << (v_l1_shift + TARGET_PAGE_BITS);
+ int rc = walk_memory_regions_1(&data, base, v_l2_levels, l1_map + i);
if (rc != 0) {
return rc;
}
--
2.7.4
- [Qemu-devel] [PULL 02/32] exec.c: Remove static allocation of sub_section of sub_page, (continued)
- [Qemu-devel] [PULL 02/32] exec.c: Remove static allocation of sub_section of sub_page, Peter Maydell, 2016/10/24
- [Qemu-devel] [PULL 28/32] hw/arm: QOM'ify pxa2xx_gpio.c, Peter Maydell, 2016/10/24
- [Qemu-devel] [PULL 08/32] hw/ptimer: Add "wraparound after one period" policy, Peter Maydell, 2016/10/24
- [Qemu-devel] [PULL 05/32] migration/savevm.c: migrate non-default page size, Peter Maydell, 2016/10/24
- [Qemu-devel] [PULL 19/32] tests: ptimer: Replace 10000 with 1, Peter Maydell, 2016/10/24
- [Qemu-devel] [PULL 17/32] tests: ptimer: Add tests for "no counter round down" policy, Peter Maydell, 2016/10/24
- [Qemu-devel] [PULL 15/32] tests: ptimer: Add tests for "no immediate reload" policy, Peter Maydell, 2016/10/24
- [Qemu-devel] [PULL 32/32] i2c: Add asserts for second smbus i2c_start_transfer(), Peter Maydell, 2016/10/24
- [Qemu-devel] [PULL 09/32] tests: ptimer: Add tests for "wraparound after one period" policy, Peter Maydell, 2016/10/24
- [Qemu-devel] [PULL 04/32] cpu: Support a target CPU having a variable page size, Peter Maydell, 2016/10/24
- [Qemu-devel] [PULL 03/32] translate-all.c: Compute L1 page table properties at runtime,
Peter Maydell <=
- Re: [Qemu-devel] [PULL 00/32] target-arm queue, no-reply, 2016/10/24
- Re: [Qemu-devel] [PULL 00/32] target-arm queue, Peter Maydell, 2016/10/25