[Date Prev][Date Next][Thread Prev][Thread Next][Date Index][Thread Index]
[Qemu-devel] [PATCH 10/16] target-m68k: suba/adda can manage word operan
From: |
Laurent Vivier |
Subject: |
[Qemu-devel] [PATCH 10/16] target-m68k: suba/adda can manage word operand |
Date: |
Wed, 26 Oct 2016 18:36:00 +0200 |
Signed-off-by: Laurent Vivier <address@hidden>
Reviewed-by: Richard Henderson <address@hidden>
---
target-m68k/translate.c | 5 +++--
1 file changed, 3 insertions(+), 2 deletions(-)
diff --git a/target-m68k/translate.c b/target-m68k/translate.c
index 28c6d93..557f671 100644
--- a/target-m68k/translate.c
+++ b/target-m68k/translate.c
@@ -2011,7 +2011,7 @@ DISAS_INSN(suba)
TCGv src;
TCGv reg;
- SRC_EA(env, src, OS_LONG, 0, NULL);
+ SRC_EA(env, src, (insn & 0x100) ? OS_LONG : OS_WORD, 1, NULL);
reg = AREG(insn, 9);
tcg_gen_sub_i32(reg, reg, src);
}
@@ -2211,7 +2211,7 @@ DISAS_INSN(adda)
TCGv src;
TCGv reg;
- SRC_EA(env, src, OS_LONG, 0, NULL);
+ SRC_EA(env, src, (insn & 0x100) ? OS_LONG : OS_WORD, 1, NULL);
reg = AREG(insn, 9);
tcg_gen_add_i32(reg, reg, src);
}
@@ -3359,6 +3359,7 @@ void register_m68k_insns (CPUM68KState *env)
INSN(subx_reg, 9100, f138, M68000);
INSN(subx_mem, 9108, f138, M68000);
INSN(suba, 91c0, f1c0, CF_ISA_A);
+ INSN(suba, 90c0, f0c0, M68000);
BASE(undef_mac, a000, f000);
INSN(mac, a000, f100, CF_EMAC);
--
2.7.4
- [Qemu-devel] [PATCH 00/16] 680x0 instruction set, part 1, Laurent Vivier, 2016/10/26
- [Qemu-devel] [PATCH 06/16] target-m68k: add addressing modes to not, Laurent Vivier, 2016/10/26
- [Qemu-devel] [PATCH 09/16] target-m68k: and can manage word and byte operands, Laurent Vivier, 2016/10/26
- [Qemu-devel] [PATCH 02/16] target-m68k: add linkl, Laurent Vivier, 2016/10/26
- [Qemu-devel] [PATCH 08/16] target-m68k: or can manage word and byte operands, Laurent Vivier, 2016/10/26
- [Qemu-devel] [PATCH 10/16] target-m68k: suba/adda can manage word operand,
Laurent Vivier <=
- [Qemu-devel] [PATCH 14/16] target-m68k: add/sub manage word and byte operands, Laurent Vivier, 2016/10/26
- [Qemu-devel] [PATCH 13/16] target-m68k: add addressing modes to neg, Laurent Vivier, 2016/10/26
- [Qemu-devel] [PATCH 04/16] target-m68k: add scc/dbcc, Laurent Vivier, 2016/10/26
- [Qemu-devel] [PATCH 11/16] target-m68k: some bit ops cleanup, Laurent Vivier, 2016/10/26
- [Qemu-devel] [PATCH 07/16] target-m68k: eor can manage word and byte operands, Laurent Vivier, 2016/10/26
- [Qemu-devel] [PATCH 12/16] target-m68k: introduce byte and word cc_ops, Laurent Vivier, 2016/10/26
- [Qemu-devel] [PATCH 01/16] target-m68k: add bkpt instruction, Laurent Vivier, 2016/10/26