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[Qemu-devel] [PATCH v2 09/17] target-m68k: or can manage word and byte o
From: |
Laurent Vivier |
Subject: |
[Qemu-devel] [PATCH v2 09/17] target-m68k: or can manage word and byte operands |
Date: |
Thu, 27 Oct 2016 02:42:22 +0200 |
Signed-off-by: Laurent Vivier <address@hidden>
Reviewed-by: Richard Henderson <address@hidden>
---
target-m68k/translate.c | 14 ++++++++------
1 file changed, 8 insertions(+), 6 deletions(-)
diff --git a/target-m68k/translate.c b/target-m68k/translate.c
index 9734d05..a6aaf5e 100644
--- a/target-m68k/translate.c
+++ b/target-m68k/translate.c
@@ -1989,19 +1989,21 @@ DISAS_INSN(or)
TCGv dest;
TCGv src;
TCGv addr;
+ int opsize;
- reg = DREG(insn, 9);
+ opsize = insn_opsize(insn);
+ reg = gen_extend(DREG(insn, 9), opsize, 0);
dest = tcg_temp_new();
if (insn & 0x100) {
- SRC_EA(env, src, OS_LONG, 0, &addr);
+ SRC_EA(env, src, opsize, 0, &addr);
tcg_gen_or_i32(dest, src, reg);
- DEST_EA(env, insn, OS_LONG, dest, &addr);
+ DEST_EA(env, insn, opsize, dest, &addr);
} else {
- SRC_EA(env, src, OS_LONG, 0, NULL);
+ SRC_EA(env, src, opsize, 0, NULL);
tcg_gen_or_i32(dest, src, reg);
- tcg_gen_mov_i32(reg, dest);
+ gen_partset_reg(opsize, DREG(insn, 9), dest);
}
- gen_logic_cc(s, dest, OS_LONG);
+ gen_logic_cc(s, dest, opsize);
}
DISAS_INSN(suba)
--
2.7.4
- [Qemu-devel] [PATCH v2 00/17] 680x0 instruction set, part 1, Laurent Vivier, 2016/10/26
- [Qemu-devel] [PATCH v2 02/17] target-m68k: add linkl, Laurent Vivier, 2016/10/26
- [Qemu-devel] [PATCH v2 03/17] target-m68k: add exg ops, Laurent Vivier, 2016/10/26
- [Qemu-devel] [PATCH v2 01/17] target-m68k: add bkpt instruction, Laurent Vivier, 2016/10/26
- [Qemu-devel] [PATCH v2 07/17] target-m68k: add addressing modes to not, Laurent Vivier, 2016/10/26
- [Qemu-devel] [PATCH v2 05/17] target-m68k: add dbcc, Laurent Vivier, 2016/10/26
- [Qemu-devel] [PATCH v2 06/17] target-m68k: Inline addx, subx, negx, Laurent Vivier, 2016/10/26
- [Qemu-devel] [PATCH v2 08/17] target-m68k: eor can manage word and byte operands, Laurent Vivier, 2016/10/26
- [Qemu-devel] [PATCH v2 09/17] target-m68k: or can manage word and byte operands,
Laurent Vivier <=
- [Qemu-devel] [PATCH v2 04/17] target-m68k: add addressing modes to scc, Laurent Vivier, 2016/10/26
- [Qemu-devel] [PATCH v2 10/17] target-m68k: and can manage word and byte operands, Laurent Vivier, 2016/10/26
- [Qemu-devel] [PATCH v2 16/17] target-m68k: cmp manages word and bytes operands, Laurent Vivier, 2016/10/26
- [Qemu-devel] [PATCH v2 14/17] target-m68k: add addressing modes to neg, Laurent Vivier, 2016/10/26
- [Qemu-devel] [PATCH v2 17/17] target-m68k: immediate ops manage word and byte operands, Laurent Vivier, 2016/10/26
- [Qemu-devel] [PATCH v2 15/17] target-m68k: add/sub manage word and byte operands, Laurent Vivier, 2016/10/26
- [Qemu-devel] [PATCH v2 12/17] target-m68k: some bit ops cleanup, Laurent Vivier, 2016/10/26
- [Qemu-devel] [PATCH v2 11/17] target-m68k: suba/adda can manage word operand, Laurent Vivier, 2016/10/26
- [Qemu-devel] [PATCH v2 13/17] target-m68k: introduce byte and word cc_ops, Laurent Vivier, 2016/10/26