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[Qemu-devel] [PATCH v2 12/17] target-m68k: some bit ops cleanup
From: |
Laurent Vivier |
Subject: |
[Qemu-devel] [PATCH v2 12/17] target-m68k: some bit ops cleanup |
Date: |
Thu, 27 Oct 2016 02:42:25 +0200 |
Signed-off-by: Laurent Vivier <address@hidden>
Reviewed-by: Richard Henderson <address@hidden>
---
target-m68k/translate.c | 34 +++++++++++++++-------------------
1 file changed, 15 insertions(+), 19 deletions(-)
diff --git a/target-m68k/translate.c b/target-m68k/translate.c
index b82ebf3..cf9b228 100644
--- a/target-m68k/translate.c
+++ b/target-m68k/translate.c
@@ -1290,39 +1290,36 @@ DISAS_INSN(bitop_reg)
else
opsize = OS_LONG;
op = (insn >> 6) & 3;
-
- gen_flush_flags(s);
-
SRC_EA(env, src1, opsize, 0, op ? &addr: NULL);
- src2 = DREG(insn, 9);
- dest = tcg_temp_new();
- tmp = tcg_temp_new();
+ gen_flush_flags(s);
+ src2 = tcg_temp_new();
if (opsize == OS_BYTE)
- tcg_gen_andi_i32(tmp, src2, 7);
+ tcg_gen_andi_i32(src2, DREG(insn, 9), 7);
else
- tcg_gen_andi_i32(tmp, src2, 31);
+ tcg_gen_andi_i32(src2, DREG(insn, 9), 31);
- src2 = tcg_const_i32(1);
- tcg_gen_shl_i32(src2, src2, tmp);
- tcg_temp_free(tmp);
+ tmp = tcg_const_i32(1);
+ tcg_gen_shl_i32(tmp, tmp, src2);
+ tcg_temp_free(src2);
- tcg_gen_and_i32(QREG_CC_Z, src1, src2);
+ tcg_gen_and_i32(QREG_CC_Z, src1, tmp);
+ dest = tcg_temp_new();
switch (op) {
case 1: /* bchg */
- tcg_gen_xor_i32(dest, src1, src2);
+ tcg_gen_xor_i32(dest, src1, tmp);
break;
case 2: /* bclr */
- tcg_gen_andc_i32(dest, src1, src2);
+ tcg_gen_andc_i32(dest, src1, tmp);
break;
case 3: /* bset */
- tcg_gen_or_i32(dest, src1, src2);
+ tcg_gen_or_i32(dest, src1, tmp);
break;
default: /* btst */
break;
}
- tcg_temp_free(src2);
+ tcg_temp_free(tmp);
if (op) {
DEST_EA(env, insn, opsize, dest, &addr);
}
@@ -1406,17 +1403,16 @@ DISAS_INSN(bitop_im)
return;
}
- gen_flush_flags(s);
-
SRC_EA(env, src1, opsize, 0, op ? &addr: NULL);
+ gen_flush_flags(s);
if (opsize == OS_BYTE)
bitnum &= 7;
else
bitnum &= 31;
mask = 1 << bitnum;
- tcg_gen_andi_i32(QREG_CC_Z, src1, mask);
+ tcg_gen_andi_i32(QREG_CC_Z, src1, mask);
if (op) {
tmp = tcg_temp_new();
--
2.7.4
- [Qemu-devel] [PATCH v2 06/17] target-m68k: Inline addx, subx, negx, (continued)
- [Qemu-devel] [PATCH v2 06/17] target-m68k: Inline addx, subx, negx, Laurent Vivier, 2016/10/26
- [Qemu-devel] [PATCH v2 08/17] target-m68k: eor can manage word and byte operands, Laurent Vivier, 2016/10/26
- [Qemu-devel] [PATCH v2 09/17] target-m68k: or can manage word and byte operands, Laurent Vivier, 2016/10/26
- [Qemu-devel] [PATCH v2 04/17] target-m68k: add addressing modes to scc, Laurent Vivier, 2016/10/26
- [Qemu-devel] [PATCH v2 10/17] target-m68k: and can manage word and byte operands, Laurent Vivier, 2016/10/26
- [Qemu-devel] [PATCH v2 16/17] target-m68k: cmp manages word and bytes operands, Laurent Vivier, 2016/10/26
- [Qemu-devel] [PATCH v2 14/17] target-m68k: add addressing modes to neg, Laurent Vivier, 2016/10/26
- [Qemu-devel] [PATCH v2 17/17] target-m68k: immediate ops manage word and byte operands, Laurent Vivier, 2016/10/26
- [Qemu-devel] [PATCH v2 15/17] target-m68k: add/sub manage word and byte operands, Laurent Vivier, 2016/10/26
- [Qemu-devel] [PATCH v2 12/17] target-m68k: some bit ops cleanup,
Laurent Vivier <=
- [Qemu-devel] [PATCH v2 11/17] target-m68k: suba/adda can manage word operand, Laurent Vivier, 2016/10/26
- [Qemu-devel] [PATCH v2 13/17] target-m68k: introduce byte and word cc_ops, Laurent Vivier, 2016/10/26