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[Qemu-devel] [PATCH v3 00/15] target-sparc improvements
From: |
Richard Henderson |
Subject: |
[Qemu-devel] [PATCH v3 00/15] target-sparc improvements |
Date: |
Thu, 27 Oct 2016 10:07:17 -0700 |
The two main goals in this patch set are:
* Make use of the new MO_ALIGN_* flags, to allow less use of check_align,
and support partially misaligned fp memory ops.
* More cleanups for ASIs, in the end using the new atomic ops.
Changes since v2:
* Rebased on master with the atomic patches merged; one minor conflict fixed.
* In patch 11, move and simplify address_mask. It's no longer used
at all by sparc32 and clang warned about the unused inline function.
Changes since v1:
* The "Remove asi helper code handled inline" patch retains the code within
ldda to handle asis that must be handled out of line. This fixes the
FreeBSD 10.3 boot problem. While the UA2007 spec (and thus sun4v?) doesn't
allow for such, it would seem that US2 hardware does.
* Dropped the "Optimize writeback of cpu_cond" patch. This fixes the
debian 7.8 install. Not sure exactly what's wrong with it yet, but
let's just drop it for now.
Mark, you gave your Tested-by to v2. Do you want to take the
patch set yourself and send the pull? Do you want to give me
a Reviewed-by and have me send the pull?
r~
Richard Henderson (15):
target-sparc: Use overalignment flags for twinx and block asis
target-sparc: Introduce cpu_raise_exception_ra
target-sparc: Add MMU_PHYS_IDX
target-sparc: Use MMU_PHYS_IDX for bypass asis
target-sparc: Handle more twinx asis
target-sparc: Implement swap_asi inline
target-sparc: Implement ldstub_asi inline
target-sparc: Implement cas_asi/casx_asi inline
target-sparc: Implement BCOPY/BFILL inline
target-sparc: Remove asi helper code handled inline
target-sparc: Implement ldqf and stqf inline
target-sparc: Allow 4-byte alignment on fp mem ops
target-sparc: Remove MMU_MODE*_SUFFIX
target-sparc: Use tcg_gen_atomic_xchg_tl
target-sparc: Use tcg_gen_atomic_cmpxchg_tl
target-sparc/cpu.h | 34 +-
target-sparc/helper.c | 52 +--
target-sparc/helper.h | 7 -
target-sparc/ldst_helper.c | 1021 ++++++++------------------------------------
target-sparc/mmu_helper.c | 47 +-
target-sparc/translate.c | 434 ++++++++++++-------
target-sparc/win_helper.c | 37 +-
7 files changed, 540 insertions(+), 1092 deletions(-)
--
2.7.4
- [Qemu-devel] [PATCH v3 00/15] target-sparc improvements,
Richard Henderson <=
- [Qemu-devel] [PATCH v3 01/15] target-sparc: Use overalignment flags for twinx and block asis, Richard Henderson, 2016/10/27
- [Qemu-devel] [PATCH v3 03/15] target-sparc: Add MMU_PHYS_IDX, Richard Henderson, 2016/10/27
- [Qemu-devel] [PATCH v3 02/15] target-sparc: Introduce cpu_raise_exception_ra, Richard Henderson, 2016/10/27
- [Qemu-devel] [PATCH v3 04/15] target-sparc: Use MMU_PHYS_IDX for bypass asis, Richard Henderson, 2016/10/27
- [Qemu-devel] [PATCH v3 05/15] target-sparc: Handle more twinx asis, Richard Henderson, 2016/10/27
- [Qemu-devel] [PATCH v3 06/15] target-sparc: Implement swap_asi inline, Richard Henderson, 2016/10/27
- [Qemu-devel] [PATCH v3 07/15] target-sparc: Implement ldstub_asi inline, Richard Henderson, 2016/10/27
- [Qemu-devel] [PATCH v3 08/15] target-sparc: Implement cas_asi/casx_asi inline, Richard Henderson, 2016/10/27
- [Qemu-devel] [PATCH v3 14/15] target-sparc: Use tcg_gen_atomic_xchg_tl, Richard Henderson, 2016/10/27
- [Qemu-devel] [PATCH v3 09/15] target-sparc: Implement BCOPY/BFILL inline, Richard Henderson, 2016/10/27