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[Qemu-devel] [PULL 14/18] target-m68k: add addressing modes to neg
From: |
Laurent Vivier |
Subject: |
[Qemu-devel] [PULL 14/18] target-m68k: add addressing modes to neg |
Date: |
Fri, 28 Oct 2016 10:48:28 +0200 |
Signed-off-by: Laurent Vivier <address@hidden>
Reviewed-by: Richard Henderson <address@hidden>
---
target-m68k/translate.c | 20 ++++++++++++--------
1 file changed, 12 insertions(+), 8 deletions(-)
diff --git a/target-m68k/translate.c b/target-m68k/translate.c
index aa09bd4..f7e6920 100644
--- a/target-m68k/translate.c
+++ b/target-m68k/translate.c
@@ -1631,16 +1631,20 @@ DISAS_INSN(move_from_ccr)
DISAS_INSN(neg)
{
- TCGv reg;
TCGv src1;
+ TCGv dest;
+ TCGv addr;
+ int opsize;
- reg = DREG(insn, 0);
- src1 = tcg_temp_new();
- tcg_gen_mov_i32(src1, reg);
- tcg_gen_neg_i32(reg, src1);
- gen_update_cc_add(reg, src1, OS_LONG);
- tcg_gen_setcondi_i32(TCG_COND_NE, QREG_CC_X, src1, 0);
- set_cc_op(s, CC_OP_SUBL);
+ opsize = insn_opsize(insn);
+ SRC_EA(env, src1, opsize, 1, &addr);
+ dest = tcg_temp_new();
+ tcg_gen_neg_i32(dest, src1);
+ set_cc_op(s, CC_OP_SUBB + opsize);
+ gen_update_cc_add(dest, src1, opsize);
+ tcg_gen_setcondi_i32(TCG_COND_NE, QREG_CC_X, dest, 0);
+ DEST_EA(env, insn, opsize, dest, &addr);
+ tcg_temp_free(dest);
}
static void gen_set_sr_im(DisasContext *s, uint16_t val, int ccr_only)
--
2.7.4
- [Qemu-devel] [PULL 00/18] M68k part2 patches, Laurent Vivier, 2016/10/28
- [Qemu-devel] [PULL 10/18] target-m68k: and can manage word and byte operands, Laurent Vivier, 2016/10/28
- [Qemu-devel] [PULL 05/18] target-m68k: add dbcc, Laurent Vivier, 2016/10/28
- [Qemu-devel] [PULL 02/18] target-m68k: add linkl, Laurent Vivier, 2016/10/28
- [Qemu-devel] [PULL 11/18] target-m68k: suba/adda can manage word operand, Laurent Vivier, 2016/10/28
- [Qemu-devel] [PULL 03/18] target-m68k: add exg ops, Laurent Vivier, 2016/10/28
- [Qemu-devel] [PULL 17/18] target-m68k: immediate ops manage word and byte operands, Laurent Vivier, 2016/10/28
- [Qemu-devel] [PULL 01/18] target-m68k: add bkpt instruction, Laurent Vivier, 2016/10/28
- [Qemu-devel] [PULL 07/18] target-m68k: add addressing modes to not, Laurent Vivier, 2016/10/28
- [Qemu-devel] [PULL 14/18] target-m68k: add addressing modes to neg,
Laurent Vivier <=
- [Qemu-devel] [PULL 16/18] target-m68k: cmp manages word and bytes operands, Laurent Vivier, 2016/10/28
- [Qemu-devel] [PULL 13/18] target-m68k: introduce byte and word cc_ops, Laurent Vivier, 2016/10/28
- [Qemu-devel] [PULL 18/18] MAINTAINERS: update M68K entry, Laurent Vivier, 2016/10/28
- [Qemu-devel] [PULL 09/18] target-m68k: or can manage word and byte operands, Laurent Vivier, 2016/10/28
- [Qemu-devel] [PULL 06/18] target-m68k: Inline addx, subx, negx, Laurent Vivier, 2016/10/28
- [Qemu-devel] [PULL 04/18] target-m68k: add addressing modes to scc, Laurent Vivier, 2016/10/28
- [Qemu-devel] [PULL 08/18] target-m68k: eor can manage word and byte operands, Laurent Vivier, 2016/10/28
- [Qemu-devel] [PULL 15/18] target-m68k: add/sub manage word and byte operands, Laurent Vivier, 2016/10/28
- [Qemu-devel] [PULL 12/18] target-m68k: some bit ops cleanup, Laurent Vivier, 2016/10/28
- Re: [Qemu-devel] [PULL 00/18] M68k part2 patches, Peter Maydell, 2016/10/28