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[Qemu-devel] [PULL 8/9] hw/arm/spitz: Fix reset handling
From: |
Peter Maydell |
Subject: |
[Qemu-devel] [PULL 8/9] hw/arm/spitz: Fix reset handling |
Date: |
Fri, 28 Oct 2016 15:59:23 +0100 |
From: Guenter Roeck <address@hidden>
Using the CPU reset handler for resets triggered by writing into
gpio pins other than GPIO01 is not appropriate and does not work,
since the reset triggered by writing into GPIO01 is configurable.
Use a separate reset handler for spitz to reset the entire system
and not just the CPU.
Signed-off-by: Guenter Roeck <address@hidden>
Message-id: address@hidden
Reviewed-by: Peter Maydell <address@hidden>
Signed-off-by: Peter Maydell <address@hidden>
---
hw/arm/spitz.c | 13 ++++++++++++-
1 file changed, 12 insertions(+), 1 deletion(-)
diff --git a/hw/arm/spitz.c b/hw/arm/spitz.c
index 41cc2ee..949a15a 100644
--- a/hw/arm/spitz.c
+++ b/hw/arm/spitz.c
@@ -29,6 +29,7 @@
#include "sysemu/block-backend.h"
#include "hw/sysbus.h"
#include "exec/address-spaces.h"
+#include "sysemu/sysemu.h"
#undef REG_FMT
#define REG_FMT "0x%02lx"
@@ -844,9 +845,18 @@ static void spitz_lcd_hsync_handler(void *opaque, int
line, int level)
spitz_hsync ^= 1;
}
+static void spitz_reset(void *opaque, int line, int level)
+{
+ if (level) {
+ qemu_system_reset_request();
+ }
+}
+
static void spitz_gpio_setup(PXA2xxState *cpu, int slots)
{
qemu_irq lcd_hsync;
+ qemu_irq reset;
+
/*
* Bad hack: We toggle the LCD hsync GPIO on every GPIO status
* read to satisfy broken guests that poll-wait for hsync.
@@ -867,7 +877,8 @@ static void spitz_gpio_setup(PXA2xxState *cpu, int slots)
qemu_irq_raise(qdev_get_gpio_in(cpu->gpio, SPITZ_GPIO_BAT_COVER));
/* Handle reset */
- qdev_connect_gpio_out(cpu->gpio, SPITZ_GPIO_ON_RESET, cpu->reset);
+ reset = qemu_allocate_irq(spitz_reset, cpu, 0);
+ qdev_connect_gpio_out(cpu->gpio, SPITZ_GPIO_ON_RESET, reset);
/* PCMCIA signals: card's IRQ and Card-Detect */
if (slots >= 1)
--
2.7.4
- [Qemu-devel] [PULL 0/9] target-arm queue, Peter Maydell, 2016/10/28
- [Qemu-devel] [PULL 8/9] hw/arm/spitz: Fix reset handling,
Peter Maydell <=
- [Qemu-devel] [PULL 7/9] arm: virt: add PMU property to mach-virt machine type, Peter Maydell, 2016/10/28
- [Qemu-devel] [PULL 3/9] hw/arm/pxa2xx: Set value default values for CCCR and CKEN on PXA255, Peter Maydell, 2016/10/28
- [Qemu-devel] [PULL 9/9] hw/arm/tosa: Fix reset handling, Peter Maydell, 2016/10/28
- [Qemu-devel] [PULL 5/9] char: cadence: correct reset value for baud rate registers, Peter Maydell, 2016/10/28
- [Qemu-devel] [PULL 4/9] versatilepb: do not run if user asks for more than 256MB RAM, Peter Maydell, 2016/10/28
- [Qemu-devel] [PULL 6/9] arm: Add an option to turn on/off vPMU support, Peter Maydell, 2016/10/28
- [Qemu-devel] [PULL 1/9] i.MX: Fix GPIO ISR register write, Peter Maydell, 2016/10/28
- [Qemu-devel] [PULL 2/9] arm: cubieboard: Add support for initrd, Peter Maydell, 2016/10/28
- Re: [Qemu-devel] [PULL 0/9] target-arm queue, Peter Maydell, 2016/10/31