Re: [Qemu-devel] [PATCH V3] docs: add PCIe devices placement guidelines

[Laszlo Ersek]

On 10/31/16 15:46, Marcel Apfelbaum wrote:
> Proposes best practices on how to use PCI Express/PCI device
> in PCI Express based machines and explain the reasoning behind them.
> 
> Signed-off-by: Marcel Apfelbaum <address@hidden>
> ---
> 
> Hi,
> 
> v2->v3:
>  - Addressed the comments from Andrea Bolognani and Laszlo Ersek, which are
>    much appreciated!
>  - Added links to presentations that may help the understanding of the 
> document.

[snip]

> +2.1.1 To plug a device into a pcie.0 as a Root Complex Integrated Endpoint 
> use:

The typo still isn't entirely fixed (it still says "into a pcie.0"), but
I don't think it justifies another repost in itself.

There's another instance of this typo in the document, so if you do
repost, please fix that as well (section 2.3.1).

[snip]

> +2.2.1 Plugging a PCI Express device into a PCI Express Root Port:
> +          -device 
> ioh3420,id=root_port1,slot=x[,chassis=y][,bus=pcie.0][,slot=y][,addr=z]  \
> +          -device <dev>,bus=root_port1
> +      Note that (slot, chassis) pair is mandatory and must be
> +      unique for each PCI Express Root Port.

Please remove "[,slot=y]"; it is no longer necessary. (The "slot=x"
device property has been promoted to mandatory in this version.)

[snip]

> +3. IO space issues
> +===================
> +The PCI Express Root Ports and PCI Express Downstream ports are seen by
> +Firmware/Guest OS as PCI-PCI Bridges. As required by the PCI spec, each
> +such Port should be reserved a 4K IO range for, even though only one
> +(multifunction) device can be plugged into each Port. This results in
> +poor IO space utilization.
> +
> +The firmware used by QEMU (SeaBIOS/OVMF) may try further optimizations
> +by not allocating IO space or each PCI Express Root / PCI Express

s/IO space *or* each/IO space *for* each/

With those changes:

Reviewed-by: Laszlo Ersek <address@hidden>

Thank you, Marcel!
Laszlo