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Re: [Qemu-devel] [PATCH v2] x86/cpuid:add AVX512_4VNNIW and AVX512_4FMAP
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From: |
Eduardo Habkost |
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Subject: |
Re: [Qemu-devel] [PATCH v2] x86/cpuid:add AVX512_4VNNIW and AVX512_4FMAPS features. |
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Date: |
Mon, 31 Oct 2016 15:20:44 -0200 |
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User-agent: |
Mutt/1.7.0 (2016-08-17) |
On Mon, Oct 31, 2016 at 04:27:26PM +0800, He Chen wrote:
> From: Luwei Kang <address@hidden>
>
> The spec can be found in Intel Software Developer Manual or in
> Instruction Set Extensions Programming Reference.
>
> Signed-off-by: Luwei Kang <address@hidden>
> Signed-off-by: Piotr Luc <address@hidden>
>
> ---
> Changes in v2:
> * correct TCG_7_0_EDX_FEATURES.
Reviewed-by: Eduardo Habkost <address@hidden>
Applied to x86-next with the following fixup:
diff --git a/target-i386/cpu.h b/target-i386/cpu.h
index c605724..6c6f8ae 100644
--- a/target-i386/cpu.h
+++ b/target-i386/cpu.h
@@ -631,7 +631,8 @@ typedef uint32_t FeatureWordArray[FEATURE_WORDS];
#define CPUID_7_0_ECX_RDPID (1U << 22)
#define CPUID_7_0_EDX_AVX512_4VNNIW (1U << 2) /* AVX512 Neural Network
Instructions */
-#define CPUID_7_0_EDX_AVX512_4FMAPS (1U << 3) /* AVX512 Multiply Accumulation
Single Precision */
+#define CPUID_7_0_EDX_AVX512_4FMAPS (1U << 3) /* AVX512 Multiply Accumulation
+ * Single Precision */
#define CPUID_XSAVE_XSAVEOPT (1U << 0)
#define CPUID_XSAVE_XSAVEC (1U << 1)
--
Eduardo