Re: [Qemu-devel] [PATCH v2] target-sh4: add atomic tas

[Richard Henderson]

On 11/03/2016 10:21 AM, Laurent Vivier wrote:
> Le 03/11/2016 à 17:18, Paolo Bonzini a écrit :
> > Well, tas_test "runs without error with this change", I suppose it fails
> > before?  In other words, is this patch enough to run multithreaded sh4
> > programs with qemu-user?
>
> It should,:the problem was reported by Adrian (cc:) while compiling ghc
> in qemu-sh4, but I have just tested the functionality with the softmmu
> version, not the atomicity.
>
> Adrian, could you test this patch?

It's a start, but sh4 has an interesting scheme to implement atomic sequences 
via special values in the stack pointer.  E.g. xchg is

        mova    1f, r0
        mov     sp, r1
        mov     #(0f-1f), sp
0:      mov.l   mem, out
        mov.l   in, mem
1:      mov     r1, sp

which is only atomic if you've got a UP kernel and have code in your interrupt 
entry point that recognizes the small negative value in SP to reset the PC as 
necessary.

For SH4A, there are proper load-locked/store-condition insns, but prior to that 
TAS was the only truly atomic insn.


r~