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[Qemu-devel] [PATCH v1 00/30] target-sparc: add niagara OpenSPARC T1 sun
From: |
Artyom Tarasenko |
Subject: |
[Qemu-devel] [PATCH v1 00/30] target-sparc: add niagara OpenSPARC T1 sun4v emulation |
Date: |
Fri, 4 Nov 2016 21:50:01 +0100 |
This patch series adds a Niagara OpenSPARC T1 sun4v machine.
The most important new feature: it can boot Solaris 10 / sparc64.
The machine uses a firmware released by Sun as a part of the OpenSPARC project.
The series are available under:
https://github.com/artyom-tarasenko/qemu/tree/sun4v-v1
The command line for booting Solaris 10 / sparc:
sparc64-softmmu/qemu-system-sparc64 -M niagara -L /path/to/S10image/ -nographic
-m 256 -drive if=pflash,readonly=on,file=/path/to/S10image/disk.s10hw2
More info under
http://tyom.blogspot.de/2016/10/qemu-sun4vniagara-target-went-public.html
Changes to v0:
Rebased on top of current master
Use lowercase machine name (Mark)
Fixed build on i686
Fixed user-mode build (Richard)
Fixed per review comments from Richard
Added Reviewed-by to the unmodified patches reviewed in the previous round
Artyom Tarasenko (30):
target-sparc: ignore MMU-faults if MMU is disabled in hypervisor mode
target-sparc: store cpu super- and hypervisor flags in TB
target-sparc: use explicit mmu register pointers
target-sparc: add UA2005 TTE bit #defines
target-sparc: add UltraSPARC T1 TLB #defines
target-sparc: on UA2005 don't deliver Interrupt_level_n IRQs in
hypervisor mode
target-sparc: simplify replace_tlb_entry by using TTE_PGSIZE
target-sparc: implement UA2005 scratchpad registers
target-sparc: implement UltraSPARC-T1 Strand status ASR
target-sparc: hypervisor mode takes over nucleus mode
target-sparc: implement UA2005 hypervisor traps
target-sparc: implement UA2005 GL register
target-sparc: implement UA2005 rdhpstate and wrhpstate instructions
target-sparc: fix immediate UA2005 traps
target-sparc: use direct address translation in hyperprivileged mode
target-sparc: allow priveleged ASIs in hyperprivileged mode
target-sparc: ignore writes to UA2005 CPU mondo queue register
target-sparc: replace the last tlb entry when no free entries left
target-sparc: use SparcV9MMU type for sparc64 I/D-MMUs
target-sparc: implement UA2005 TSB Pointers
target-sparc: simplify ultrasparc_tsb_pointer
target-sparc: allow 256M sized pages
target-sparc: implement auto-demapping for UA2005 CPUs
target-sparc: add more registers to dump_mmu
target-sparc: implement UA2005 ASI_MMU (0x21)
target-sparc: store the UA2005 entries in sun4u format
target-sparc: add ST_BLKINIT_ ASIs for UA2005+ CPUs
target-sparc: implement sun4v RTC
target-sparc: move common cpu initialisation routines to sparc64.c
target-sparc: fix up niagara machine
MAINTAINERS | 7 +
default-configs/sparc64-softmmu.mak | 2 +
hw/sparc64/Makefile.objs | 2 +
hw/sparc64/niagara.c | 177 +++++++++++++++++
hw/sparc64/sparc64.c | 378 +++++++++++++++++++++++++++++++++++
hw/sparc64/sun4u.c | 379 +----------------------------------
hw/timer/Makefile.objs | 2 +
hw/timer/sun4v-rtc.c | 102 ++++++++++
include/hw/sparc/sparc64.h | 5 +
include/hw/timer/sun4v-rtc.h | 1 +
linux-user/main.c | 2 +-
target-sparc/asi.h | 1 +
target-sparc/cpu.c | 13 +-
target-sparc/cpu.h | 105 +++++++---
target-sparc/helper.h | 1 +
target-sparc/int64_helper.c | 43 +++-
target-sparc/ldst_helper.c | 385 ++++++++++++++++++++++++++++--------
target-sparc/machine.c | 4 +-
target-sparc/mmu_helper.c | 20 +-
target-sparc/translate.c | 64 ++++--
target-sparc/win_helper.c | 46 ++++-
21 files changed, 1213 insertions(+), 526 deletions(-)
create mode 100644 hw/sparc64/niagara.c
create mode 100644 hw/sparc64/sparc64.c
create mode 100644 hw/timer/sun4v-rtc.c
create mode 100644 include/hw/sparc/sparc64.h
create mode 100644 include/hw/timer/sun4v-rtc.h
--
1.8.3.1
- [Qemu-devel] [PATCH v1 00/30] target-sparc: add niagara OpenSPARC T1 sun4v emulation,
Artyom Tarasenko <=
- [Qemu-devel] [PATCH v1 01/30] target-sparc: ignore MMU-faults if MMU is disabled in hypervisor mode, Artyom Tarasenko, 2016/11/04
- [Qemu-devel] [PATCH v1 02/30] target-sparc: store cpu super- and hypervisor flags in TB, Artyom Tarasenko, 2016/11/04
- [Qemu-devel] [PATCH v1 03/30] target-sparc: use explicit mmu register pointers, Artyom Tarasenko, 2016/11/04
- [Qemu-devel] [PATCH v1 04/30] target-sparc: add UA2005 TTE bit #defines, Artyom Tarasenko, 2016/11/04
- [Qemu-devel] [PATCH v1 05/30] target-sparc: add UltraSPARC T1 TLB #defines, Artyom Tarasenko, 2016/11/04
- [Qemu-devel] [PATCH v1 06/30] target-sparc: on UA2005 don't deliver Interrupt_level_n IRQs in hypervisor mode, Artyom Tarasenko, 2016/11/04
- [Qemu-devel] [PATCH v1 07/30] target-sparc: simplify replace_tlb_entry by using TTE_PGSIZE, Artyom Tarasenko, 2016/11/04