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[Qemu-devel] [PATCH v1 13/30] target-sparc: implement UA2005 rdhpstate a
From: |
Artyom Tarasenko |
Subject: |
[Qemu-devel] [PATCH v1 13/30] target-sparc: implement UA2005 rdhpstate and wrhpstate instructions |
Date: |
Fri, 4 Nov 2016 21:50:14 +0100 |
Signed-off-by: Artyom Tarasenko <address@hidden>
Reviewed-by: Richard Henderson <address@hidden>
---
target-sparc/translate.c | 7 +++++--
1 file changed, 5 insertions(+), 2 deletions(-)
diff --git a/target-sparc/translate.c b/target-sparc/translate.c
index 68677d3..7e399a3 100644
--- a/target-sparc/translate.c
+++ b/target-sparc/translate.c
@@ -3468,7 +3468,8 @@ static void disas_sparc_insn(DisasContext * dc, unsigned
int insn)
rs1 = GET_FIELD(insn, 13, 17);
switch (rs1) {
case 0: // hpstate
- // gen_op_rdhpstate();
+ tcg_gen_ld_i64(cpu_dst, cpu_env,
+ offsetof(CPUSPARCState, hpstate));
break;
case 1: // htstate
// gen_op_rdhtstate();
@@ -4592,7 +4593,9 @@ static void disas_sparc_insn(DisasContext * dc, unsigned
int insn)
tcg_gen_xor_tl(cpu_tmp0, cpu_src1, cpu_src2);
switch (rd) {
case 0: // hpstate
- // XXX gen_op_wrhpstate();
+ tcg_gen_st_i64(cpu_tmp0, cpu_env,
+ offsetof(CPUSPARCState,
+ hpstate));
save_state(dc);
gen_op_next_insn();
tcg_gen_exit_tb(0);
--
1.8.3.1
- Re: [Qemu-devel] [PATCH v1 02/30] target-sparc: store cpu super- and hypervisor flags in TB, (continued)
- [Qemu-devel] [PATCH v1 03/30] target-sparc: use explicit mmu register pointers, Artyom Tarasenko, 2016/11/04
- [Qemu-devel] [PATCH v1 04/30] target-sparc: add UA2005 TTE bit #defines, Artyom Tarasenko, 2016/11/04
- [Qemu-devel] [PATCH v1 05/30] target-sparc: add UltraSPARC T1 TLB #defines, Artyom Tarasenko, 2016/11/04
- [Qemu-devel] [PATCH v1 06/30] target-sparc: on UA2005 don't deliver Interrupt_level_n IRQs in hypervisor mode, Artyom Tarasenko, 2016/11/04
- [Qemu-devel] [PATCH v1 07/30] target-sparc: simplify replace_tlb_entry by using TTE_PGSIZE, Artyom Tarasenko, 2016/11/04
- [Qemu-devel] [PATCH v1 08/30] target-sparc: implement UA2005 scratchpad registers, Artyom Tarasenko, 2016/11/04
- [Qemu-devel] [PATCH v1 09/30] target-sparc: implement UltraSPARC-T1 Strand status ASR, Artyom Tarasenko, 2016/11/04
- [Qemu-devel] [PATCH v1 10/30] target-sparc: hypervisor mode takes over nucleus mode, Artyom Tarasenko, 2016/11/04
- [Qemu-devel] [PATCH v1 11/30] target-sparc: implement UA2005 hypervisor traps, Artyom Tarasenko, 2016/11/04
- [Qemu-devel] [PATCH v1 13/30] target-sparc: implement UA2005 rdhpstate and wrhpstate instructions,
Artyom Tarasenko <=
- [Qemu-devel] [PATCH v1 14/30] target-sparc: fix immediate UA2005 traps, Artyom Tarasenko, 2016/11/04
- [Qemu-devel] [PATCH v1 17/30] target-sparc: ignore writes to UA2005 CPU mondo queue register, Artyom Tarasenko, 2016/11/04
- [Qemu-devel] [PATCH v1 12/30] target-sparc: implement UA2005 GL register, Artyom Tarasenko, 2016/11/04
- [Qemu-devel] [PATCH v1 16/30] target-sparc: allow priveleged ASIs in hyperprivileged mode, Artyom Tarasenko, 2016/11/04
- [Qemu-devel] [PATCH v1 18/30] target-sparc: replace the last tlb entry when no free entries left, Artyom Tarasenko, 2016/11/04
- [Qemu-devel] [PATCH v1 15/30] target-sparc: use direct address translation in hyperprivileged mode, Artyom Tarasenko, 2016/11/04
- [Qemu-devel] [PATCH v1 19/30] target-sparc: use SparcV9MMU type for sparc64 I/D-MMUs, Artyom Tarasenko, 2016/11/04
- [Qemu-devel] [PATCH v1 20/30] target-sparc: implement UA2005 TSB Pointers, Artyom Tarasenko, 2016/11/04
- [Qemu-devel] [PATCH v1 21/30] target-sparc: simplify ultrasparc_tsb_pointer, Artyom Tarasenko, 2016/11/04
- [Qemu-devel] [PATCH v1 23/30] target-sparc: implement auto-demapping for UA2005 CPUs, Artyom Tarasenko, 2016/11/04