Re: [Qemu-devel] [PATCH] target-m68k: add rol/ror/roxl/roxr instructions

[Richard Henderson]

On 11/09/2016 07:47 PM, Richard Henderson wrote:
> On 11/09/2016 06:30 PM, Laurent Vivier wrote:
> > +        /* create [src:X:..] */
> > +
> > +        tcg_gen_deposit_i32(t0, QREG_CC_X, src, 1, size);
> > +        tcg_gen_shli_i32(t0, t0, 31 - size);
> > +
> > +        /* rotate */
> > +
> > +        tcg_gen_rotl_i32(t0, t0, shift);
> > +
> > +        /* result is [src:..:src:X] */
> > +
> > +        tcg_gen_andi_i32(X, t0, 1);
> > +        tcg_gen_shri_i32(t0, t0, 1);
>
> I don't see how this is supposed to work.  If you form [src:x:...], and rotate
> by 0, then X gets garbage.  Of course, you're actually forming [0:src:x].  But
> for a rol of 2, the lsb of src gets 0's instead of the msb of src.
>
> If you want to use a 32-bit rotate here, you have to (1) reduce the rotate by
> modulo size + 1 and (2) form [src:...:src:x].  E.g.
>
>     tcg_gen_deposit_i32(t0, Q_REG_CC_X, src, 32 - size, size);
>     tcg_gen_deposit_i32(t0, t0, src, 1, size);

Feh, actually that only works for rot8, since you need 2*size+1 bits available 
for this.  Why not just use shifts.  Something like

  int shl = shift % 17;
  int shr = shl ^ (size - 1);
  int shx = shl ? shl - 1 : 16;

  res32 = (data << shl) | (data >> shr) | (x << shx);
  x = (res32 >> 16) & 1;


r~