Re: [Qemu-devel] [PATCH] target-m68k: Implement bfffo

[Laurent Vivier]

Le 15/11/2016 à 21:44, Richard Henderson a écrit :
> Signed-off-by: Richard Henderson <address@hidden>
> ---
> 
> I've started a glibc test run with this, but I don't expect overmuch.
> The only applications I can see are "bfffo *,0,32,dN" which isn't
> exactly exhaustive.  Probably better to hand craft some tests vs real
> hardware.
> 
> Considering the prevelance of small helper functions calling ctz/clz,
> I'm thinking of adding an opcode to tcg for this.  Certainly all of
> the common hosts support it natively...

I've booted an etch-m68k container with patch and it works.

> @@ -3943,11 +3960,17 @@ DISAS_INSN(bfop_reg)
>              tcg_gen_rotl_i32(QREG_CC_N, src, tmp);
>              tcg_gen_andc_i32(QREG_CC_N, QREG_CC_N, mask);
>              tcg_gen_rotr_i32(mask, mask, tmp);
> +            if (!TCGV_IS_UNUSED(tofs)) {
> +                tcg_gen_mov_tl(tofs, tmp);

_tl suffix is never used with m68k, should we?


> @@ -5415,6 +5450,8 @@ void register_m68k_insns (CPUM68KState *env)
>      INSN(bfop_reg, eac0, fff8, BITFIELD);   /* bfchg */
>      INSN(bfop_mem, ecc0, ffc0, BITFIELD);   /* bfclr */
>      INSN(bfop_reg, ecc0, fff8, BITFIELD);   /* bfclr */
> +    INSN(bfop_mem, edc0, ffc0, BITFIELD);   /* bfffo */
> +    INSN(bfop_reg, edc0, fff8, BITFIELD);   /* bfffo */

In my doc, bfffo is 0xE9C0.

Thanks,
Laurent