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Re: [Qemu-devel] [PATCH 8/9] target-ppc: add vextu[bhw]lx instructions
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From: |
David Gibson |
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Subject: |
Re: [Qemu-devel] [PATCH 8/9] target-ppc: add vextu[bhw]lx instructions |
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Date: |
Wed, 23 Nov 2016 15:11:09 +1100 |
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User-agent: |
Mutt/1.7.1 (2016-10-04) |
On Tue, Nov 22, 2016 at 05:16:04PM +0530, Nikunj A Dadhania wrote:
> From: Avinesh Kumar <address@hidden>
>
> vextublx: Vector Extract Unsigned Byte Left
> vextuhlx: Vector Extract Unsigned Halfword Left
> vextuwlx: Vector Extract Unsigned Word Left
>
> Signed-off-by: Avinesh Kumar <address@hidden>
> Signed-off-by: Nikunj A Dadhania <address@hidden>
> ---
> target-ppc/helper.h | 3 ++
> target-ppc/int_helper.c | 63
> +++++++++++++++++++++++++++++++++++++
> target-ppc/translate/vmx-impl.inc.c | 18 +++++++++++
> target-ppc/translate/vmx-ops.inc.c | 4 ++-
> 4 files changed, 87 insertions(+), 1 deletion(-)
>
> diff --git a/target-ppc/helper.h b/target-ppc/helper.h
> index 3b26678..d0a8fb2 100644
> --- a/target-ppc/helper.h
> +++ b/target-ppc/helper.h
> @@ -366,6 +366,9 @@ DEF_HELPER_3(vpmsumb, void, avr, avr, avr)
> DEF_HELPER_3(vpmsumh, void, avr, avr, avr)
> DEF_HELPER_3(vpmsumw, void, avr, avr, avr)
> DEF_HELPER_3(vpmsumd, void, avr, avr, avr)
> +DEF_HELPER_2(vextublx, tl, tl, avr)
> +DEF_HELPER_2(vextuhlx, tl, tl, avr)
> +DEF_HELPER_2(vextuwlx, tl, tl, avr)
>
> DEF_HELPER_2(vsbox, void, avr, avr)
> DEF_HELPER_3(vcipher, void, avr, avr, avr)
> diff --git a/target-ppc/int_helper.c b/target-ppc/int_helper.c
> index 8886a72..fb9f178 100644
> --- a/target-ppc/int_helper.c
> +++ b/target-ppc/int_helper.c
> @@ -1805,6 +1805,69 @@ void helper_vlogefp(CPUPPCState *env, ppc_avr_t *r,
> ppc_avr_t *b)
> }
> }
>
> +#define EXTRACT128(value, start, length) \
> + ((value >> start) & (~(__uint128_t)0 >> (128 - length)))
Although we do use 128-bit arithmetic in some places in qemu, I don't
think we assume the presence of a working uint1238_t type. Better to
actually write a helper function which does this in terms of 64 bit
arithmetic, I think.
> +
> +#if defined(HOST_WORDS_BIGENDIAN)
> +# if defined(CONFIG_INT128)
> +# define VEXTULX_DO(name, elem) \
> +target_ulong glue(helper_, name)(target_ulong a, ppc_avr_t *b) \
It seems a bit odd to need helpers for what's essentially just copying
a byte/halfword/whatever out of the vector.
> +{ \
> + target_ulong r = 0; \
> + int index = (a & 0xf) * 8; \
> + r = EXTRACT128(b->u128, index, elem * 8); \
> + return r; \
> +}
> +# else
> +# define VEXTULX_DO(name, elem) \
> +target_ulong glue(helper_, name)(target_ulong a, ppc_avr_t *b) \
> +{ \
> + target_ulong r = 0; \
> + int i; \
> + int index = a & 0xf; \
> + for (i = 0; i < elem; i++) { \
> + r = r << 8; \
> + if (index + i <= 15) { \
> + r = r | b->u8[index + i]; \
> + } \
> + } \
> + return r; \
> +}
> +# endif
> +#else
> +# if defined(CONFIG_INT128)
> +# define VEXTULX_DO(name, elem) \
> +target_ulong glue(helper_, name)(target_ulong a, ppc_avr_t *b) \
> +{ \
> + target_ulong r = 0; \
> + int size = elem * 8; \
> + int index = (15 - (a & 0xf) + 1) * 8; \
> + r = EXTRACT128(b->u128, (index - size), size); \
> + return r; \
> +}
> +# else
> +# define VEXTULX_DO(name, elem) \
> +target_ulong glue(helper_, name)(target_ulong a, ppc_avr_t *b) \
> +{ \
> + target_ulong r = 0; \
> + int i; \
> + int index = 15 - (a & 0xf); \
> + for (i = 0; i < elem; i++) { \
> + r = r << 8; \
> + if (index - i >= 0) { \
> + r = r | b->u8[index - i]; \
> + } \
> + } \
> + return r; \
> +}
> +# endif
> +#endif
> +
> +VEXTULX_DO(vextublx, 1)
> +VEXTULX_DO(vextuhlx, 2)
> +VEXTULX_DO(vextuwlx, 4)
> +#undef VEXTULX_DO
> +
> /* The specification says that the results are undefined if all of the
> * shift counts are not identical. We check to make sure that they are
> * to conform to what real hardware appears to do. */
> diff --git a/target-ppc/translate/vmx-impl.inc.c
> b/target-ppc/translate/vmx-impl.inc.c
> index 7143eb3..e91d10b 100644
> --- a/target-ppc/translate/vmx-impl.inc.c
> +++ b/target-ppc/translate/vmx-impl.inc.c
> @@ -340,6 +340,19 @@ static void glue(gen_, name0##_##name1)(DisasContext
> *ctx) \
> } \
> }
>
> +#define GEN_VXFORM_HETRO(name, opc2, opc3) \
> +static void glue(gen_, name)(DisasContext *ctx) \
> +{ \
> + TCGv_ptr rb; \
> + if (unlikely(!ctx->altivec_enabled)) { \
> + gen_exception(ctx, POWERPC_EXCP_VPU); \
> + return; \
> + } \
> + rb = gen_avr_ptr(rB(ctx->opcode)); \
> + gen_helper_##name(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)],
> rb); \
> + tcg_temp_free_ptr(rb); \
> +}
> +
> GEN_VXFORM(vaddubm, 0, 0);
> GEN_VXFORM_DUAL_EXT(vaddubm, PPC_ALTIVEC, PPC_NONE, 0, \
> vmul10cuq, PPC_NONE, PPC2_ISA300, 0x0000F800)
> @@ -525,6 +538,11 @@ GEN_VXFORM_ENV(vaddfp, 5, 0);
> GEN_VXFORM_ENV(vsubfp, 5, 1);
> GEN_VXFORM_ENV(vmaxfp, 5, 16);
> GEN_VXFORM_ENV(vminfp, 5, 17);
> +GEN_VXFORM_HETRO(vextublx, 6, 24)
> +GEN_VXFORM_HETRO(vextuhlx, 6, 25)
> +GEN_VXFORM_HETRO(vextuwlx, 6, 26)
> +GEN_VXFORM_DUAL(vmrgow, PPC_NONE, PPC2_ALTIVEC_207,
> + vextuwlx, PPC_NONE, PPC2_ISA300)
>
> #define GEN_VXRFORM1(opname, name, str, opc2, opc3) \
> static void glue(gen_, name)(DisasContext *ctx) \
> diff --git a/target-ppc/translate/vmx-ops.inc.c
> b/target-ppc/translate/vmx-ops.inc.c
> index f02b3be..e62e564 100644
> --- a/target-ppc/translate/vmx-ops.inc.c
> +++ b/target-ppc/translate/vmx-ops.inc.c
> @@ -91,8 +91,10 @@ GEN_VXFORM(vmrghw, 6, 2),
> GEN_VXFORM(vmrglb, 6, 4),
> GEN_VXFORM(vmrglh, 6, 5),
> GEN_VXFORM(vmrglw, 6, 6),
> +GEN_VXFORM_300(vextublx, 6, 24),
> +GEN_VXFORM_300(vextuhlx, 6, 25),
> +GEN_VXFORM_DUAL(vmrgow, vextuwlx, 6, 26, PPC_NONE, PPC2_ALTIVEC_207),
> GEN_VXFORM_207(vmrgew, 6, 30),
> -GEN_VXFORM_207(vmrgow, 6, 26),
> GEN_VXFORM(vmuloub, 4, 0),
> GEN_VXFORM(vmulouh, 4, 1),
> GEN_VXFORM_DUAL(vmulouw, vmuluwm, 4, 2, PPC_ALTIVEC, PPC_NONE),
--
David Gibson | I'll have my music baroque, and my code
david AT gibson.dropbear.id.au | minimalist, thank you. NOT _the_ _other_
| _way_ _around_!
http://www.ozlabs.org/~dgibson
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- Re: [Qemu-devel] [PATCH 2/9] target-ppc: Fix xscmpodp and xscmpudp instructions, (continued)
[Qemu-devel] [PATCH 3/9] target-ppc: Add xscmpexp[dp, qp] instructions, Nikunj A Dadhania, 2016/11/22
[Qemu-devel] [PATCH 9/9] target-ppc: add vextu[bhw]rx instructions, Nikunj A Dadhania, 2016/11/22
[Qemu-devel] [PATCH 7/9] target-ppc: implement lxv/lxvx and stxv/stxvx, Nikunj A Dadhania, 2016/11/22
[Qemu-devel] [PATCH 6/9] target-ppc: implement stxsd and stxssp, Nikunj A Dadhania, 2016/11/22
[Qemu-devel] [PATCH 8/9] target-ppc: add vextu[bhw]lx instructions, Nikunj A Dadhania, 2016/11/22
- Re: [Qemu-devel] [PATCH 8/9] target-ppc: add vextu[bhw]lx instructions,
David Gibson <=
[Qemu-devel] [PATCH 5/9] target-ppc: implement lxsd and lxssp instructions, Nikunj A Dadhania, 2016/11/22
[Qemu-devel] [PATCH 4/9] target-ppc: Add xscmpoqp and xscmpuqp instructions, Nikunj A Dadhania, 2016/11/22