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[Qemu-devel] [PATCH v4 41/64] tcg/aarch64: Handle ctz and clz opcodes
From: |
Richard Henderson |
Subject: |
[Qemu-devel] [PATCH v4 41/64] tcg/aarch64: Handle ctz and clz opcodes |
Date: |
Wed, 23 Nov 2016 14:01:38 +0100 |
Signed-off-by: Richard Henderson <address@hidden>
---
tcg/aarch64/tcg-target.h | 8 ++++----
tcg/aarch64/tcg-target.inc.c | 47 ++++++++++++++++++++++++++++++++++++++++++++
2 files changed, 51 insertions(+), 4 deletions(-)
diff --git a/tcg/aarch64/tcg-target.h b/tcg/aarch64/tcg-target.h
index 976f493..9d6b00f 100644
--- a/tcg/aarch64/tcg-target.h
+++ b/tcg/aarch64/tcg-target.h
@@ -62,8 +62,8 @@ typedef enum {
#define TCG_TARGET_HAS_eqv_i32 1
#define TCG_TARGET_HAS_nand_i32 0
#define TCG_TARGET_HAS_nor_i32 0
-#define TCG_TARGET_HAS_clz_i32 0
-#define TCG_TARGET_HAS_ctz_i32 0
+#define TCG_TARGET_HAS_clz_i32 1
+#define TCG_TARGET_HAS_ctz_i32 1
#define TCG_TARGET_HAS_deposit_i32 1
#define TCG_TARGET_HAS_extract_i32 1
#define TCG_TARGET_HAS_sextract_i32 1
@@ -96,8 +96,8 @@ typedef enum {
#define TCG_TARGET_HAS_eqv_i64 1
#define TCG_TARGET_HAS_nand_i64 0
#define TCG_TARGET_HAS_nor_i64 0
-#define TCG_TARGET_HAS_clz_i64 0
-#define TCG_TARGET_HAS_ctz_i64 0
+#define TCG_TARGET_HAS_clz_i64 1
+#define TCG_TARGET_HAS_ctz_i64 1
#define TCG_TARGET_HAS_deposit_i64 1
#define TCG_TARGET_HAS_extract_i64 1
#define TCG_TARGET_HAS_sextract_i64 1
diff --git a/tcg/aarch64/tcg-target.inc.c b/tcg/aarch64/tcg-target.inc.c
index 17c0b20..91345fc 100644
--- a/tcg/aarch64/tcg-target.inc.c
+++ b/tcg/aarch64/tcg-target.inc.c
@@ -201,6 +201,9 @@ static int tcg_target_const_match(tcg_target_long val,
TCGType type,
if ((ct & TCG_CT_CONST_MONE) && val == -1) {
return 1;
}
+ if ((ct & TCG_CT_CONST_WSZ) && val == (type ? 64 : 32)) {
+ return 1;
+ }
return 0;
}
@@ -339,8 +342,12 @@ typedef enum {
/* Conditional select instructions. */
I3506_CSEL = 0x1a800000,
I3506_CSINC = 0x1a800400,
+ I3506_CSINV = 0x5a800000,
+ I3506_CSNEG = 0x5a800400,
/* Data-processing (1 source) instructions. */
+ I3507_CLZ = 0x5ac01000,
+ I3507_RBIT = 0x5ac00000,
I3507_REV16 = 0x5ac00400,
I3507_REV32 = 0x5ac00800,
I3507_REV64 = 0x5ac00c00,
@@ -993,6 +1000,32 @@ static inline void tcg_out_mb(TCGContext *s, TCGArg a0)
tcg_out32(s, sync[a0 & TCG_MO_ALL]);
}
+static void tcg_out_clz(TCGContext *s, TCGType ext, TCGReg d,
+ TCGReg a, TCGArg b, bool const_b)
+{
+ if (const_b && b == (ext ? 64 : 32)) {
+ tcg_out_insn(s, 3507, CLZ, ext, d, a);
+ } else {
+ AArch64Insn sel = I3506_CSEL;
+
+ tcg_out_cmp(s, ext, a, 0, 1);
+ tcg_out_insn(s, 3507, CLZ, ext, TCG_REG_TMP, a);
+
+ if (const_b) {
+ if (b == -1) {
+ b = TCG_REG_XZR;
+ sel = I3506_CSINV;
+ } else if (b == 0) {
+ b = TCG_REG_XZR;
+ } else {
+ tcg_out_movi(s, ext, d, b);
+ b = d;
+ }
+ }
+ tcg_out_insn_3506(s, sel, ext, d, TCG_REG_TMP, b, TCG_COND_NE);
+ }
+}
+
#ifdef CONFIG_SOFTMMU
/* helper signature: helper_ret_ld_mmu(CPUState *env, target_ulong addr,
* TCGMemOpIdx oi, uintptr_t ra)
@@ -1559,6 +1592,16 @@ static void tcg_out_op(TCGContext *s, TCGOpcode opc,
}
break;
+ case INDEX_op_clz_i64:
+ case INDEX_op_clz_i32:
+ tcg_out_clz(s, ext, a0, a1, a2, c2);
+ break;
+ case INDEX_op_ctz_i64:
+ case INDEX_op_ctz_i32:
+ tcg_out_insn(s, 3507, RBIT, ext, TCG_REG_TMP, a1);
+ tcg_out_clz(s, ext, a0, TCG_REG_TMP, a2, c2);
+ break;
+
case INDEX_op_brcond_i32:
a1 = (int32_t)a1;
/* FALLTHRU */
@@ -1750,11 +1793,15 @@ static const TCGTargetOpDef aarch64_op_defs[] = {
{ INDEX_op_sar_i32, { "r", "r", "ri" } },
{ INDEX_op_rotl_i32, { "r", "r", "ri" } },
{ INDEX_op_rotr_i32, { "r", "r", "ri" } },
+ { INDEX_op_clz_i32, { "r", "r", "rAL" } },
+ { INDEX_op_ctz_i32, { "r", "r", "rAL" } },
{ INDEX_op_shl_i64, { "r", "r", "ri" } },
{ INDEX_op_shr_i64, { "r", "r", "ri" } },
{ INDEX_op_sar_i64, { "r", "r", "ri" } },
{ INDEX_op_rotl_i64, { "r", "r", "ri" } },
{ INDEX_op_rotr_i64, { "r", "r", "ri" } },
+ { INDEX_op_clz_i64, { "r", "r", "rAL" } },
+ { INDEX_op_ctz_i64, { "r", "r", "rAL" } },
{ INDEX_op_brcond_i32, { "r", "rA" } },
{ INDEX_op_brcond_i64, { "r", "rA" } },
--
2.7.4
- [Qemu-devel] [PATCH v4 31/64] target-openrisc: Use clz and ctz opcodes, (continued)
- [Qemu-devel] [PATCH v4 31/64] target-openrisc: Use clz and ctz opcodes, Richard Henderson, 2016/11/23
- [Qemu-devel] [PATCH v4 30/64] target-mips: Use clz opcode, Richard Henderson, 2016/11/23
- [Qemu-devel] [PATCH v4 32/64] target-ppc: Use clz and ctz opcodes, Richard Henderson, 2016/11/23
- [Qemu-devel] [PATCH v4 33/64] target-s390x: Use clz opcode, Richard Henderson, 2016/11/23
- [Qemu-devel] [PATCH v4 34/64] target-tilegx: Use clz and ctz opcodes, Richard Henderson, 2016/11/23
- [Qemu-devel] [PATCH v4 36/64] target-unicore32: Use clz opcode, Richard Henderson, 2016/11/23
- [Qemu-devel] [PATCH v4 35/64] target-tricore: Use clz opcode, Richard Henderson, 2016/11/23
- [Qemu-devel] [PATCH v4 38/64] target-arm: Use clz opcode, Richard Henderson, 2016/11/23
- [Qemu-devel] [PATCH v4 37/64] target-xtensa: Use clz opcode, Richard Henderson, 2016/11/23
- [Qemu-devel] [PATCH v4 39/64] target-i386: Use clz and ctz opcodes, Richard Henderson, 2016/11/23
- [Qemu-devel] [PATCH v4 41/64] tcg/aarch64: Handle ctz and clz opcodes,
Richard Henderson <=
- [Qemu-devel] [PATCH v4 40/64] tcg/ppc: Handle ctz and clz opcodes, Richard Henderson, 2016/11/23
- [Qemu-devel] [PATCH v4 43/64] tcg/mips: Handle clz opcode, Richard Henderson, 2016/11/23
- [Qemu-devel] [PATCH v4 42/64] tcg/arm: Handle ctz and clz opcodes, Richard Henderson, 2016/11/23
- [Qemu-devel] [PATCH v4 44/64] tcg/s390: Handle clz opcode, Richard Henderson, 2016/11/23
- [Qemu-devel] [PATCH v4 46/64] tcg/i386: Hoist common arguments in tcg_out_op, Richard Henderson, 2016/11/23
- [Qemu-devel] [PATCH v4 47/64] tcg/i386: Allow bmi2 shiftx to have non-matching operands, Richard Henderson, 2016/11/23
- [Qemu-devel] [PATCH v4 45/64] tcg/i386: Fuly convert tcg_target_op_def, Richard Henderson, 2016/11/23
- [Qemu-devel] [PATCH v4 51/64] target-arm: Use clrsb helper, Richard Henderson, 2016/11/23
- [Qemu-devel] [PATCH v4 49/64] tcg/i386: Rely on undefined/undocumented behaviour of BSF/BSR, Richard Henderson, 2016/11/23
- [Qemu-devel] [PATCH v4 48/64] tcg/i386: Handle ctz and clz opcodes, Richard Henderson, 2016/11/23