[Date Prev][Date Next][Thread Prev][Thread Next][Date Index][Thread Index]
Re: [Qemu-devel] [PATCH v1 09/10] target-ppc: add vextu[bhw]lx instructi
From: |
Nikunj A Dadhania |
Subject: |
Re: [Qemu-devel] [PATCH v1 09/10] target-ppc: add vextu[bhw]lx instructions |
Date: |
Thu, 24 Nov 2016 11:23:41 +0530 |
User-agent: |
Notmuch/0.21 (https://notmuchmail.org) Emacs/25.0.94.1 (x86_64-redhat-linux-gnu) |
David Gibson <address@hidden> writes:
> [ Unknown signature status ]
> On Wed, Nov 23, 2016 at 05:07:18PM +0530, Nikunj A Dadhania wrote:
>> From: Avinesh Kumar <address@hidden>
>>
>> vextublx: Vector Extract Unsigned Byte Left
>> vextuhlx: Vector Extract Unsigned Halfword Left
>> vextuwlx: Vector Extract Unsigned Word Left
>>
>> Signed-off-by: Avinesh Kumar <address@hidden>
>> Signed-off-by: Nikunj A Dadhania <address@hidden>
>
> So, when I suggested doing these without helpers before, I had
> forgotten that the non-byte versions can straddle the word boundary.
> Given that the offset is in a register, not the instruction that does
> make it complicated.
>
> But, this version also relies on working 128-bit arithmetic, AFAICT
> this will just fail to build if CONFIG_INT128 isn't defined.
It has both the implementation, just that the defines might have
confused you:
#if defined(HOST_WORDS_BIGENDIAN)
# if defined(CONFIG_INT128)
# else
# endif
#else /* !defined (HOST_WORDS_BIGENDIAN) */
# if defined(CONFIG_INT128)
# else
# endif
#endif
> It really shouldn't be that hard to make a helper that works just in
> terms of 64-bit arithmetic - there are only 3 cases (all in the upper
> word, all in the lower, and straddling).
Currently, its being done using byte array.
+{ \
+ target_ulong r = 0; \
+ int i; \
+ int index = a & 0xf; \
+ for (i = 0; i < elem; i++) { \
+ r = r << 8; \
+ if (index + i <= 15) { \
+ r = r | b->u8[index + i]; \
+ } \
+ } \
+ return r; \
+}
> I'd prefer to see it done that way, rather than increasing reliance on
> CONFIG_INT128.
Regards
Nikunj
- [Qemu-devel] [PATCH v1 01/10] target-ppc: Consolidate instruction decode helpers, (continued)
- [Qemu-devel] [PATCH v1 01/10] target-ppc: Consolidate instruction decode helpers, Nikunj A Dadhania, 2016/11/23
- [Qemu-devel] [PATCH v1 02/10] target-ppc: rename CRF_* defines as CRF_*_BIT, Nikunj A Dadhania, 2016/11/23
- [Qemu-devel] [PATCH v1 04/10] target-ppc: Add xscmpexp[dp, qp] instructions, Nikunj A Dadhania, 2016/11/23
- [Qemu-devel] [PATCH v1 05/10] target-ppc: Add xscmpoqp and xscmpuqp instructions, Nikunj A Dadhania, 2016/11/23
- [Qemu-devel] [PATCH v1 03/10] target-ppc: Fix xscmpodp and xscmpudp instructions, Nikunj A Dadhania, 2016/11/23
- [Qemu-devel] [PATCH v1 06/10] target-ppc: implement lxsd and lxssp instructions, Nikunj A Dadhania, 2016/11/23
- [Qemu-devel] [PATCH v1 07/10] target-ppc: implement stxsd and stxssp, Nikunj A Dadhania, 2016/11/23
- [Qemu-devel] [PATCH v1 09/10] target-ppc: add vextu[bhw]lx instructions, Nikunj A Dadhania, 2016/11/23
[Qemu-devel] [PATCH v1 08/10] target-ppc: implement lxv/lxvx and stxv/stxvx, Nikunj A Dadhania, 2016/11/23
[Qemu-devel] [PATCH v1 10/10] target-ppc: add vextu[bhw]rx instructions, Nikunj A Dadhania, 2016/11/23
Re: [Qemu-devel] [PATCH v1 ppc-for-2.9 00/10] POWER9 TCG enablements - part8, David Gibson, 2016/11/23