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[Qemu-devel] [PATCH v3 11/11] tcg-mips: Adjust condition functions for m
From: |
Jin Guojie |
Subject: |
[Qemu-devel] [PATCH v3 11/11] tcg-mips: Adjust condition functions for mips64 |
Date: |
Fri, 25 Nov 2016 11:31:44 +0800 |
32-bit condition functions(like brcond_i32) should only
compare the low half parts of two 64-bit host registers.
However, MIPS64 does not have distinct instruction for
such operation. The operands should be sign extended
to fit the case.
Gcc handles 32-bit comparison in the same way, as the
following example shows:
[a.c]
main()
{
long a = 0xcccccccc;
long b = 0xdddddddd;
int c = (int)a > (int)b;
}
$ gcc a.c -S -mabi=64
$ vi a.s
.......
sd $2,0($fp)
sd $3,8($fp)
lw $2,0($fp)
lw $3,8($fp)
slt $1,$2,$3
........
Cc: Aurelien Jarno <address@hidden>
Cc: James Hogan <address@hidden>
Signed-off-by: Richard Henderson <address@hidden>
Signed-off-by: Jin Guojie <address@hidden>
---
tcg/mips/tcg-target.inc.c | 20 ++++++++++++++++++++
1 file changed, 20 insertions(+)
diff --git a/tcg/mips/tcg-target.inc.c b/tcg/mips/tcg-target.inc.c
index 95090b6..0eb48ce 100644
--- a/tcg/mips/tcg-target.inc.c
+++ b/tcg/mips/tcg-target.inc.c
@@ -696,6 +696,11 @@ static inline void tcg_out_ext32u(TCGContext *s, TCGReg
ret, TCGReg arg)
}
}
+static inline void tcg_out_ext32s(TCGContext *s, TCGReg ret, TCGReg arg)
+{
+ tcg_out_opc_reg(s, OPC_ADDU, ret, arg, TCG_REG_ZERO);
+}
+
static void tcg_out_ldst(TCGContext *s, MIPSInsn opc, TCGReg data,
TCGReg addr, intptr_t ofs)
{
@@ -2023,6 +2028,11 @@ static inline void tcg_out_op(TCGContext *s, TCGOpcode
opc,
break;
case INDEX_op_brcond_i32:
+#if TCG_TARGET_REG_BITS == 64
+ tcg_out_ext32s(s, a0, a0);
+ tcg_out_ext32s(s, a1, a1);
+ /* FALLTHRU */
+#endif
case INDEX_op_brcond_i64:
tcg_out_brcond(s, a2, a0, a1, arg_label(args[3]));
break;
@@ -2031,11 +2041,21 @@ static inline void tcg_out_op(TCGContext *s, TCGOpcode
opc,
break;
case INDEX_op_movcond_i32:
+#if TCG_TARGET_REG_BITS == 64
+ tcg_out_ext32s(s, a1, a1);
+ tcg_out_ext32s(s, a2, a2);
+ /* FALLTHRU */
+#endif
case INDEX_op_movcond_i64:
tcg_out_movcond(s, args[5], a0, a1, a2, args[3], args[4]);
break;
case INDEX_op_setcond_i32:
+#if TCG_TARGET_REG_BITS == 64
+ tcg_out_ext32s(s, a1, a1);
+ tcg_out_ext32s(s, a2, a2);
+ /* FALLTHRU */
+#endif
case INDEX_op_setcond_i64:
tcg_out_setcond(s, args[3], a0, a1, a2);
break;
--
2.1.0
- [Qemu-devel] [PATCH v3 00/11] tcg mips64 and mips r6 improvements, Jin Guojie, 2016/11/24
- [Qemu-devel] [PATCH v3 01/11] tcg-mips: Move bswap code to a subroutine, Jin Guojie, 2016/11/24
- [Qemu-devel] [PATCH v3 02/11] tcg-mips: Add mips64 opcodes, Jin Guojie, 2016/11/24
- [Qemu-devel] [PATCH v3 03/11] tcg-mips: Support 64-bit opcodes, Jin Guojie, 2016/11/24
- [Qemu-devel] [PATCH v3 04/11] tcg-mips: Add bswap32u and bswap64, Jin Guojie, 2016/11/24
- [Qemu-devel] [PATCH v3 05/11] tcg-mips: Adjust move functions for mips64, Jin Guojie, 2016/11/24
- [Qemu-devel] [PATCH v3 06/11] tcg-mips: Adjust load/store functions for mips64, Jin Guojie, 2016/11/24
- [Qemu-devel] [PATCH v3 08/11] tcg-mips: Add tcg unwind info, Jin Guojie, 2016/11/24
- [Qemu-devel] [PATCH v3 09/11] tcg-mips: Adjust calling conventions for mips64, Jin Guojie, 2016/11/24
- [Qemu-devel] [PATCH v3 07/11] tcg-mips: Adjust prologue for mips64, Jin Guojie, 2016/11/24
- [Qemu-devel] [PATCH v3 11/11] tcg-mips: Adjust condition functions for mips64,
Jin Guojie <=
- [Qemu-devel] [PATCH v3 10/11] tcg-mips: Adjust qemu_ld/st for mips64, Jin Guojie, 2016/11/24
- Re: [Qemu-devel] [PATCH v3 00/11] tcg mips64 and mips r6 improvements, Aurelien Jarno, 2016/11/25
- Re: [Qemu-devel] [PATCH v3 00/11] tcg mips64 and mips r6 improvements, Aurelien Jarno, 2016/11/30