Re: [Qemu-devel] [PATCH v4 10/10] tcg-mips: Adjust qemu_ld/st for mips64

[Aurelien Jarno]

On 2016-11-30 09:42, Richard Henderson wrote:
> On 11/30/2016 09:22 AM, Aurelien Jarno wrote:
> > On 2016-11-29 14:07, Jin Guojie wrote:
> >> @@ -1312,7 +1340,12 @@ static void tcg_out_qemu_ld_slow_path(TCGContext 
> >> *s, TCGLabelQemuLdst *l)
> >>      reloc_pc16(s->code_ptr, l->raddr);
> >>      tcg_out_opc_br(s, OPC_BEQ, TCG_REG_ZERO, TCG_REG_ZERO);
> >>      /* delay slot */
> >> -    tcg_out_mov(s, TCG_TYPE_REG, v0, TCG_REG_V0);
> >> +    if (TCG_TARGET_REG_BITS == 64 && l->type == TCG_TYPE_I32) {
> >> +        /* we always sign-extend 32-bit loads */
> >> +        tcg_out_opc_sa(s, OPC_SLL, v0, TCG_REG_V0, 0);
> >> +    } else {
> >> +        tcg_out_opc_reg(s, OPC_OR, v0, TCG_REG_V0, TCG_REG_ZERO);
> >> +    }
> > 
> > While thoses are equivalent, I think it would be clearer to keep the
> > original version for the else case (ie tcg_out_mov) instead of replacing
> > it by a OR instruction.
> 
> Did we exclude v0 from the registers that can be used?
> Otherwise we do need to ensure that some insn gets placed in the delay slot.

Hmm, that's a good point. Also note that the original code didn't check
about that, so it was probably not working in some cases. I guess we can
therefore leave the code like that for now.

-- 
Aurelien Jarno                          GPG: 4096R/1DDD8C9B
address@hidden                 http://www.aurel32.net