Re: [Qemu-devel] [PATCH 1/2] tcg/aarch64: Fix addsub2 for 0+C

[Richard Henderson]

On 12/07/2016 10:10 AM, Peter Maydell wrote:
> On 7 December 2016 at 18:07, Richard Henderson <address@hidden> wrote:
>> When al == xzr, we cannot use addi/subi because that encodes xsp.
>> Force a zero into the temp register for that (rare) case.
> 
> Incidentally I was slightly surprised that the optimisation
> pass didn't turn "add2 rlo, rhi, 0, 0, 0, 0" into moves of 0
> into rlo and rhi. Constant shifts of xzr in the guest don't
> seem worth spending much effort on optimising though :-)

Until this last release cycle, we couldn't insert opcodes into the instruction
stream during optimization.  Thus we were very restricted in what we could do
when wanting to assign simpler values to two different outputs.

I'll bet addition of 0 + non-constant come up semi-regularly for 32-bit hosts
and 64-bit guests.  I'll see about better simplification of double-word
arithmetic for the next cycle.


r~