Re: [Qemu-devel] [PATCH] target-i386: Add Intel SHA_NI instruction support.

[Paolo Bonzini]

On 14/12/2016 03:50, Yi Sun wrote:
> Add SHA_NI feature bit. Its spec can be found at:
> https://software.intel.com/sites/default/files/managed/39/c5/325462-sdm-vol-1-2abcd-3abcd.pdf
> 
> Signed-off-by: Yi Sun <address@hidden>
> ---
>  target-i386/cpu.c | 2 +-
>  target-i386/cpu.h | 1 +
>  2 files changed, 2 insertions(+), 1 deletion(-)
> 
> diff --git a/target-i386/cpu.c b/target-i386/cpu.c
> index de1f30e..993f825 100644
> --- a/target-i386/cpu.c
> +++ b/target-i386/cpu.c
> @@ -422,7 +422,7 @@ static FeatureWordInfo feature_word_info[FEATURE_WORDS] = 
> {
>              "avx512f", "avx512dq", "rdseed", "adx",
>              "smap", "avx512ifma", "pcommit", "clflushopt",
>              "clwb", NULL, "avx512pf", "avx512er",
> -            "avx512cd", NULL, "avx512bw", "avx512vl",
> +            "avx512cd", "sha-ni", "avx512bw", "avx512vl",
>          },
>          .cpuid_eax = 7,
>          .cpuid_needs_ecx = true, .cpuid_ecx = 0,
> diff --git a/target-i386/cpu.h b/target-i386/cpu.h
> index c605724..d0bf624 100644
> --- a/target-i386/cpu.h
> +++ b/target-i386/cpu.h
> @@ -621,6 +621,7 @@ typedef uint32_t FeatureWordArray[FEATURE_WORDS];
>  #define CPUID_7_0_EBX_AVX512PF (1U << 26) /* AVX-512 Prefetch */
>  #define CPUID_7_0_EBX_AVX512ER (1U << 27) /* AVX-512 Exponential and 
> Reciprocal */
>  #define CPUID_7_0_EBX_AVX512CD (1U << 28) /* AVX-512 Conflict Detection */
> +#define CPUID_7_0_EBX_SHA_NI   (1U << 29) /* SHA1/SHA256 Instruction 
> Extensions */
>  #define CPUID_7_0_EBX_AVX512BW (1U << 30) /* AVX-512 Byte and Word 
> Instructions */
>  #define CPUID_7_0_EBX_AVX512VL (1U << 31) /* AVX-512 Vector Length 
> Extensions */
>  
> 

Looks good, thanks.

Paolo