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[Qemu-devel] [PULL 07/25] target-arm: Log AArch64 exception returns
From: |
Peter Maydell |
Subject: |
[Qemu-devel] [PULL 07/25] target-arm: Log AArch64 exception returns |
Date: |
Tue, 27 Dec 2016 15:20:59 +0000 |
We already log exception entry; add logging of the AArch64 exception
return path as well.
Signed-off-by: Peter Maydell <address@hidden>
Reviewed-by: Edgar E. Iglesias <address@hidden>
---
target/arm/op_helper.c | 9 +++++++++
1 file changed, 9 insertions(+)
diff --git a/target/arm/op_helper.c b/target/arm/op_helper.c
index cd94216..ba796d8 100644
--- a/target/arm/op_helper.c
+++ b/target/arm/op_helper.c
@@ -17,6 +17,7 @@
* License along with this library; if not, see <http://www.gnu.org/licenses/>.
*/
#include "qemu/osdep.h"
+#include "qemu/log.h"
#include "cpu.h"
#include "exec/helper-proto.h"
#include "internals.h"
@@ -972,6 +973,9 @@ void HELPER(exception_return)(CPUARMState *env)
} else {
env->regs[15] = env->elr_el[cur_el] & ~0x3;
}
+ qemu_log_mask(CPU_LOG_INT, "Exception return from AArch64 EL%d to "
+ "AArch32 EL%d PC 0x%" PRIx32 "\n",
+ cur_el, new_el, env->regs[15]);
} else {
env->aarch64 = 1;
pstate_write(env, spsr);
@@ -980,6 +984,9 @@ void HELPER(exception_return)(CPUARMState *env)
}
aarch64_restore_sp(env, new_el);
env->pc = env->elr_el[cur_el];
+ qemu_log_mask(CPU_LOG_INT, "Exception return from AArch64 EL%d to "
+ "AArch64 EL%d PC 0x%" PRIx64 "\n",
+ cur_el, new_el, env->pc);
}
arm_call_el_change_hook(arm_env_get_cpu(env));
@@ -1002,6 +1009,8 @@ illegal_return:
if (!arm_singlestep_active(env)) {
env->pstate &= ~PSTATE_SS;
}
+ qemu_log_mask(LOG_GUEST_ERROR, "Illegal exception return at EL%d: "
+ "resuming execution at 0x%" PRIx64 "\n", cur_el, env->pc);
}
/* Return true if the linked breakpoint entry lbn passes its checks */
--
2.7.4
- [Qemu-devel] [PULL 00/25] target-arm queue, Peter Maydell, 2016/12/27
- [Qemu-devel] [PULL 01/25] cadence_uart: Check baud rate generator and divider values on migration, Peter Maydell, 2016/12/27
- [Qemu-devel] [PULL 02/25] cadence_uart: Check if receiver timeout counter is disabled, Peter Maydell, 2016/12/27
- [Qemu-devel] [PULL 03/25] Correct value of ARM Cortex-A8 MVFR1 register., Peter Maydell, 2016/12/27
- [Qemu-devel] [PULL 04/25] target-arm: Fix aarch64 vec_reg_offset, Peter Maydell, 2016/12/27
- [Qemu-devel] [PULL 05/25] target-arm: Fix aarch64 disas_ldst_single_struct, Peter Maydell, 2016/12/27
- [Qemu-devel] [PULL 06/25] hw/intc/arm_gicv3_common: fix aff3 in typer, Peter Maydell, 2016/12/27
- [Qemu-devel] [PULL 07/25] target-arm: Log AArch64 exception returns,
Peter Maydell <=
- [Qemu-devel] [PULL 08/25] hw/intc/arm_gicv3: Remove incorrect usage of fieldoffset, Peter Maydell, 2016/12/27
- [Qemu-devel] [PULL 09/25] hw/intc/arm_gicv3: Don't signal Pending+Active interrupts to CPU, Peter Maydell, 2016/12/27
- [Qemu-devel] [PULL 10/25] hw/arm/virt: add 2.9 machine type, Peter Maydell, 2016/12/27
- [Qemu-devel] [PULL 11/25] m25p80: add support for the mx66l1g45g, Peter Maydell, 2016/12/27
- [Qemu-devel] [PULL 12/25] aspeed: QOMify the CPU object and attach it to the SoC, Peter Maydell, 2016/12/27
- [Qemu-devel] [PULL 13/25] aspeed: remove cannot_destroy_with_object_finalize_yet, Peter Maydell, 2016/12/27
- [Qemu-devel] [PULL 14/25] aspeed: attach the second SPI controller object to the SoC, Peter Maydell, 2016/12/27
- [Qemu-devel] [PULL 15/25] aspeed: extend the board configuration with flash models, Peter Maydell, 2016/12/27
- [Qemu-devel] [PULL 16/25] aspeed: add support for the romulus-bmc board, Peter Maydell, 2016/12/27
- [Qemu-devel] [PULL 17/25] aspeed: add a memory region for SRAM, Peter Maydell, 2016/12/27