Re: [Qemu-devel] [PATCH v3] [i.MX] fix CS handling during SPI access.

[mar.krzeminski]

W dniu 06.01.2017 o 19:18, Jean-Christophe DUBOIS pisze:
> Le 06/01/2017 à 13:28, mar.krzeminski a écrit :
> > > > Please make sure that in HW ECSPI_CONFIGREG_SS_POL bits are 0's 
> > > > after reset/power up (defaults).
> > >
> > > There is already a memset to 0 of all regs (including CONFIGREG) in 
> > > the reset function.
> > I saw that memset, my question is rather real HW also have 0s after 
> > reset (could be important
> > in some cases).
>
> Yes, all registers are set to 0 at reset except STATREG which is set 
> to 3 (according to reference manual).
Thanks!
> > Thanks,
> > Marcin