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[Qemu-devel] [PATCH 10/11] target-ppc: Add xvxsigdp instruction
From: |
Nikunj A Dadhania |
Subject: |
[Qemu-devel] [PATCH 10/11] target-ppc: Add xvxsigdp instruction |
Date: |
Tue, 10 Jan 2017 14:20:42 +0530 |
xvxsigdp: VSX Vector Extract Significand Dual Precision
Signed-off-by: Nikunj A Dadhania <address@hidden>
---
target/ppc/translate/vsx-impl.inc.c | 40 +++++++++++++++++++++++++++++++++++++
target/ppc/translate/vsx-ops.inc.c | 1 +
2 files changed, 41 insertions(+)
diff --git a/target/ppc/translate/vsx-impl.inc.c
b/target/ppc/translate/vsx-impl.inc.c
index 4e57af7..7e068a4 100644
--- a/target/ppc/translate/vsx-impl.inc.c
+++ b/target/ppc/translate/vsx-impl.inc.c
@@ -1432,6 +1432,46 @@ static void gen_xvxexpdp(DisasContext *ctx)
GEN_VSX_HELPER_2(xvxsigsp, 0x00, 0x04, 0, PPC2_ISA300)
+static void gen_xvxsigdp(DisasContext *ctx)
+{
+ TCGv_i64 xth = cpu_vsrh(xT(ctx->opcode));
+ TCGv_i64 xtl = cpu_vsrl(xT(ctx->opcode));
+ TCGv_i64 xbh = cpu_vsrh(xB(ctx->opcode));
+ TCGv_i64 xbl = cpu_vsrl(xB(ctx->opcode));
+
+ TCGv_i64 t0, zr, nan, exp;
+
+ if (unlikely(!ctx->vsx_enabled)) {
+ gen_exception(ctx, POWERPC_EXCP_VSXU);
+ return;
+ }
+ exp = tcg_temp_new_i64();
+ t0 = tcg_temp_new_i64();
+ zr = tcg_const_i64(0);
+ nan = tcg_const_i64(2047);
+
+ tcg_gen_shri_i64(exp, xbh, 52);
+ tcg_gen_andi_i64(exp, exp, 0x7FF);
+ tcg_gen_movi_i64(t0, 0x0010000000000000);
+ tcg_gen_movcond_i64(TCG_COND_EQ, t0, exp, zr, zr, t0);
+ tcg_gen_movcond_i64(TCG_COND_EQ, t0, exp, nan, zr, t0);
+ tcg_gen_andi_i64(xth, xbh, 0x000FFFFFFFFFFFFF);
+ tcg_gen_or_i64(xth, xth, t0);
+
+ tcg_gen_shri_i64(exp, xbl, 52);
+ tcg_gen_andi_i64(exp, exp, 0x7FF);
+ tcg_gen_movi_i64(t0, 0x0010000000000000);
+ tcg_gen_movcond_i64(TCG_COND_EQ, t0, exp, zr, zr, t0);
+ tcg_gen_movcond_i64(TCG_COND_EQ, t0, exp, nan, zr, t0);
+ tcg_gen_andi_i64(xtl, xbl, 0x000FFFFFFFFFFFFF);
+ tcg_gen_or_i64(xtl, xtl, t0);
+
+ tcg_temp_free_i64(t0);
+ tcg_temp_free_i64(exp);
+ tcg_temp_free_i64(zr);
+ tcg_temp_free_i64(nan);
+}
+
#undef GEN_XX2FORM
#undef GEN_XX3FORM
#undef GEN_XX2IFORM
diff --git a/target/ppc/translate/vsx-ops.inc.c
b/target/ppc/translate/vsx-ops.inc.c
index 2c4f641..367fd38 100644
--- a/target/ppc/translate/vsx-ops.inc.c
+++ b/target/ppc/translate/vsx-ops.inc.c
@@ -127,6 +127,7 @@ GEN_VSX_XFORM_300(xsiexpqp, 0x4, 0x1B, 0x00000001),
GEN_XX3FORM(xviexpsp, 0x00, 0x1B, PPC2_ISA300),
GEN_XX3FORM(xviexpdp, 0x00, 0x1F, PPC2_ISA300),
GEN_XX2FORM_EO(xvxexpdp, 0x16, 0x1D, 0x00, PPC2_ISA300),
+GEN_XX2FORM_EO(xvxsigdp, 0x16, 0x1D, 0x01, PPC2_ISA300),
GEN_XX2FORM_EO(xvxexpsp, 0x16, 0x1D, 0x08, PPC2_ISA300),
GEN_XX2FORM_EO(xvxsigsp, 0x16, 0x1D, 0x09, PPC2_ISA300),
--
2.7.4
- [Qemu-devel] [PATCH 03/11] target-ppc: Add xsiexpdp instruction, (continued)
- [Qemu-devel] [PATCH 04/11] target-ppc: Add xsiexpqp instruction, Nikunj A Dadhania, 2017/01/10
- [Qemu-devel] [PATCH 06/11] target-ppc: Add xviexpdp instruction, Nikunj A Dadhania, 2017/01/10
- [Qemu-devel] [PATCH 08/11] target-ppc: Add xvxexpdp instruction, Nikunj A Dadhania, 2017/01/10
- [Qemu-devel] [PATCH 07/11] target-ppc: Add xvxexpsp instruction, Nikunj A Dadhania, 2017/01/10
- [Qemu-devel] [PATCH 05/11] target-ppc: Add xviexpsp instruction, Nikunj A Dadhania, 2017/01/10
- [Qemu-devel] [PATCH 09/11] target-ppc: Add xvxsigsp instruction, Nikunj A Dadhania, 2017/01/10
- [Qemu-devel] [PATCH 10/11] target-ppc: Add xvxsigdp instruction,
Nikunj A Dadhania <=
- [Qemu-devel] [PATCH 11/11] target-ppc: Add xscvqps[d, w]z instructions, Nikunj A Dadhania, 2017/01/10
- Re: [Qemu-devel] [PATCH 00/11] POWER9 TCG enablements - part11, David Gibson, 2017/01/11
- Re: [Qemu-devel] [PATCH 00/11] POWER9 TCG enablements - part11, David Gibson, 2017/01/12