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[Qemu-devel] [PULL 15/65] target-i386: Use new deposit and extract ops
From: |
Richard Henderson |
Subject: |
[Qemu-devel] [PULL 15/65] target-i386: Use new deposit and extract ops |
Date: |
Tue, 10 Jan 2017 18:17:30 -0800 |
A couple of places where it was easy to identify a right-shift
followed by an extract or and-with-immediate, and the obvious
sign-extract from a high byte register.
Acked-by: Eduardo Habkost <address@hidden>
Signed-off-by: Richard Henderson <address@hidden>
---
target/i386/translate.c | 45 +++++++++++++++++++++++----------------------
1 file changed, 23 insertions(+), 22 deletions(-)
diff --git a/target/i386/translate.c b/target/i386/translate.c
index 59e11fc..816d0b1 100644
--- a/target/i386/translate.c
+++ b/target/i386/translate.c
@@ -383,8 +383,7 @@ static void gen_op_mov_reg_v(TCGMemOp ot, int reg, TCGv t0)
static inline void gen_op_mov_v_reg(TCGMemOp ot, TCGv t0, int reg)
{
if (ot == MO_8 && byte_reg_is_xH(reg)) {
- tcg_gen_shri_tl(t0, cpu_regs[reg - 4], 8);
- tcg_gen_ext8u_tl(t0, t0);
+ tcg_gen_extract_tl(t0, cpu_regs[reg - 4], 8, 8);
} else {
tcg_gen_mov_tl(t0, cpu_regs[reg]);
}
@@ -3768,8 +3767,7 @@ static void gen_sse(CPUX86State *env, DisasContext *s,
int b,
/* Extract the LEN into a mask. Lengths larger than
operand size get all ones. */
- tcg_gen_shri_tl(cpu_A0, cpu_regs[s->vex_v], 8);
- tcg_gen_ext8u_tl(cpu_A0, cpu_A0);
+ tcg_gen_extract_tl(cpu_A0, cpu_regs[s->vex_v], 8, 8);
tcg_gen_movcond_tl(TCG_COND_LEU, cpu_A0, cpu_A0, bound,
cpu_A0, bound);
tcg_temp_free(bound);
@@ -3920,9 +3918,8 @@ static void gen_sse(CPUX86State *env, DisasContext *s,
int b,
gen_compute_eflags(s);
}
carry_in = cpu_tmp0;
- tcg_gen_shri_tl(carry_in, cpu_cc_src,
- ctz32(b == 0x1f6 ? CC_C : CC_O));
- tcg_gen_andi_tl(carry_in, carry_in, 1);
+ tcg_gen_extract_tl(carry_in, cpu_cc_src,
+ ctz32(b == 0x1f6 ? CC_C : CC_O), 1);
}
switch (ot) {
@@ -5447,21 +5444,25 @@ static target_ulong disas_insn(CPUX86State *env,
DisasContext *s,
rm = (modrm & 7) | REX_B(s);
if (mod == 3) {
- gen_op_mov_v_reg(ot, cpu_T0, rm);
- switch (s_ot) {
- case MO_UB:
- tcg_gen_ext8u_tl(cpu_T0, cpu_T0);
- break;
- case MO_SB:
- tcg_gen_ext8s_tl(cpu_T0, cpu_T0);
- break;
- case MO_UW:
- tcg_gen_ext16u_tl(cpu_T0, cpu_T0);
- break;
- default:
- case MO_SW:
- tcg_gen_ext16s_tl(cpu_T0, cpu_T0);
- break;
+ if (s_ot == MO_SB && byte_reg_is_xH(rm)) {
+ tcg_gen_sextract_tl(cpu_T0, cpu_regs[rm - 4], 8, 8);
+ } else {
+ gen_op_mov_v_reg(ot, cpu_T0, rm);
+ switch (s_ot) {
+ case MO_UB:
+ tcg_gen_ext8u_tl(cpu_T0, cpu_T0);
+ break;
+ case MO_SB:
+ tcg_gen_ext8s_tl(cpu_T0, cpu_T0);
+ break;
+ case MO_UW:
+ tcg_gen_ext16u_tl(cpu_T0, cpu_T0);
+ break;
+ default:
+ case MO_SW:
+ tcg_gen_ext16s_tl(cpu_T0, cpu_T0);
+ break;
+ }
}
gen_op_mov_reg_v(d_ot, reg, cpu_T0);
} else {
--
2.9.3
- [Qemu-devel] [PULL 11/65] tcg/s390: Implement field extraction opcodes, (continued)
- [Qemu-devel] [PULL 11/65] tcg/s390: Implement field extraction opcodes, Richard Henderson, 2017/01/10
- [Qemu-devel] [PULL 10/65] tcg/s390: Expose host facilities to tcg-target.h, Richard Henderson, 2017/01/10
- [Qemu-devel] [PULL 13/65] target-alpha: Use deposit and extract ops, Richard Henderson, 2017/01/10
- [Qemu-devel] [PULL 19/65] tcg/optimize: Fold movcond 0/1 into setcond, Richard Henderson, 2017/01/10
- [Qemu-devel] [PULL 14/65] target-arm: Use new deposit and extract ops, Richard Henderson, 2017/01/10
- [Qemu-devel] [PULL 15/65] target-i386: Use new deposit and extract ops,
Richard Henderson <=
- [Qemu-devel] [PULL 16/65] target-mips: Use the new extract op, Richard Henderson, 2017/01/10
- [Qemu-devel] [PULL 17/65] target-ppc: Use the new deposit and extract ops, Richard Henderson, 2017/01/10
- [Qemu-devel] [PULL 18/65] target-s390x: Use the new deposit and extract ops, Richard Henderson, 2017/01/10
- [Qemu-devel] [PULL 20/65] tcg: Add markup for output requires new register, Richard Henderson, 2017/01/10
- [Qemu-devel] [PULL 21/65] tcg: Transition flat op_defs array to a target callback, Richard Henderson, 2017/01/10
- [Qemu-devel] [PULL 23/65] tcg: Allow an operand to be matching or a constant, Richard Henderson, 2017/01/10
- [Qemu-devel] [PULL 22/65] tcg: Pass the opcode width to target_parse_constraint, Richard Henderson, 2017/01/10
- [Qemu-devel] [PULL 26/65] disas/ppc: Handle popcnt and cnttz, Richard Henderson, 2017/01/10
- [Qemu-devel] [PULL 25/65] disas/i386.c: Handle tzcnt, Richard Henderson, 2017/01/10
- [Qemu-devel] [PULL 27/65] target-alpha: Use the ctz and clz opcodes, Richard Henderson, 2017/01/10