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[Qemu-devel] [PULL 25/65] disas/i386.c: Handle tzcnt
From: |
Richard Henderson |
Subject: |
[Qemu-devel] [PULL 25/65] disas/i386.c: Handle tzcnt |
Date: |
Tue, 10 Jan 2017 18:17:40 -0800 |
Signed-off-by: Richard Henderson <address@hidden>
---
disas/i386.c | 12 ++++++++++--
1 file changed, 10 insertions(+), 2 deletions(-)
diff --git a/disas/i386.c b/disas/i386.c
index 57145d0..07f871f 100644
--- a/disas/i386.c
+++ b/disas/i386.c
@@ -682,6 +682,7 @@ fetch_data(struct disassemble_info *info, bfd_byte *addr)
#define PREGRP104 NULL, { { NULL, USE_PREFIX_USER_TABLE }, { NULL, 104 } }
#define PREGRP105 NULL, { { NULL, USE_PREFIX_USER_TABLE }, { NULL, 105 } }
#define PREGRP106 NULL, { { NULL, USE_PREFIX_USER_TABLE }, { NULL, 106 } }
+#define PREGRP107 NULL, { { NULL, USE_PREFIX_USER_TABLE }, { NULL, 107 } }
#define X86_64_0 NULL, { { NULL, X86_64_SPECIAL }, { NULL, 0 } }
#define X86_64_1 NULL, { { NULL, X86_64_SPECIAL }, { NULL, 1 } }
@@ -1247,7 +1248,7 @@ static const struct dis386 dis386_twobyte[] = {
{ "ud2b", { XX } },
{ GRP8 },
{ "btcS", { Ev, Gv } },
- { "bsfS", { Gv, Ev } },
+ { PREGRP107 },
{ PREGRP36 },
{ "movs{bR|x|bR|x}", { Gv, Eb } },
{ "movs{wR|x|wR|x}", { Gv, Ew } }, /* yes, there really is movsww ! */
@@ -1431,7 +1432,7 @@ static const unsigned char twobyte_uses_REPZ_prefix[256]
= {
/* 80 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 8f */
/* 90 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 9f */
/* a0 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* af */
- /* b0 */ 0,0,0,0,0,0,0,0,1,0,0,0,0,1,0,0, /* bf */
+ /* b0 */ 0,0,0,0,0,0,0,0,1,0,0,0,1,1,0,0, /* bf */
/* c0 */ 0,0,1,0,0,0,0,0,0,0,0,0,0,0,0,0, /* cf */
/* d0 */ 0,0,0,0,0,0,1,0,0,0,0,0,0,0,0,0, /* df */
/* e0 */ 0,0,0,0,0,0,1,0,0,0,0,0,0,0,0,0, /* ef */
@@ -2800,6 +2801,13 @@ static const struct dis386 prefix_user_table[][4] = {
{ "shrxS", { Gv, Ev, Bv } },
},
+ /* PREGRP107 */
+ {
+ { "bsfS", { Gv, Ev } },
+ { "tzcntS", { Gv, Ev } },
+ { "bsfS", { Gv, Ev } },
+ { "(bad)", { XX } },
+ },
};
static const struct dis386 x86_64_table[][2] = {
--
2.9.3
- [Qemu-devel] [PULL 14/65] target-arm: Use new deposit and extract ops, (continued)
- [Qemu-devel] [PULL 14/65] target-arm: Use new deposit and extract ops, Richard Henderson, 2017/01/10
- [Qemu-devel] [PULL 15/65] target-i386: Use new deposit and extract ops, Richard Henderson, 2017/01/10
- [Qemu-devel] [PULL 16/65] target-mips: Use the new extract op, Richard Henderson, 2017/01/10
- [Qemu-devel] [PULL 17/65] target-ppc: Use the new deposit and extract ops, Richard Henderson, 2017/01/10
- [Qemu-devel] [PULL 18/65] target-s390x: Use the new deposit and extract ops, Richard Henderson, 2017/01/10
- [Qemu-devel] [PULL 20/65] tcg: Add markup for output requires new register, Richard Henderson, 2017/01/10
- [Qemu-devel] [PULL 21/65] tcg: Transition flat op_defs array to a target callback, Richard Henderson, 2017/01/10
- [Qemu-devel] [PULL 23/65] tcg: Allow an operand to be matching or a constant, Richard Henderson, 2017/01/10
- [Qemu-devel] [PULL 22/65] tcg: Pass the opcode width to target_parse_constraint, Richard Henderson, 2017/01/10
- [Qemu-devel] [PULL 26/65] disas/ppc: Handle popcnt and cnttz, Richard Henderson, 2017/01/10
- [Qemu-devel] [PULL 25/65] disas/i386.c: Handle tzcnt,
Richard Henderson <=
- [Qemu-devel] [PULL 27/65] target-alpha: Use the ctz and clz opcodes, Richard Henderson, 2017/01/10
- [Qemu-devel] [PULL 29/65] target-microblaze: Use clz opcode, Richard Henderson, 2017/01/10
- [Qemu-devel] [PULL 28/65] target-cris: Use clz opcode, Richard Henderson, 2017/01/10
- [Qemu-devel] [PULL 24/65] tcg: Add clz and ctz opcodes, Richard Henderson, 2017/01/10
- [Qemu-devel] [PULL 30/65] target-mips: Use clz opcode, Richard Henderson, 2017/01/10
- [Qemu-devel] [PULL 31/65] target-openrisc: Use clz and ctz opcodes, Richard Henderson, 2017/01/10
- [Qemu-devel] [PULL 34/65] target-tilegx: Use clz and ctz opcodes, Richard Henderson, 2017/01/10
- [Qemu-devel] [PULL 33/65] target-s390x: Use clz opcode, Richard Henderson, 2017/01/10
- [Qemu-devel] [PULL 36/65] target-unicore32: Use clz opcode, Richard Henderson, 2017/01/10
- [Qemu-devel] [PULL 38/65] target-arm: Use clz opcode, Richard Henderson, 2017/01/10