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[Qemu-devel] [PATCH v2 15/30] target-sparc: use direct address translati
From: |
Artyom Tarasenko |
Subject: |
[Qemu-devel] [PATCH v2 15/30] target-sparc: use direct address translation in hyperprivileged mode |
Date: |
Wed, 11 Jan 2017 21:19:46 +0100 |
Please note that QEMU doesn't impelement Real->Physical address
translation. The "Real Address" is always the "Physical Address".
Suggested-by: Richard Henderson <address@hidden>
Signed-off-by: Artyom Tarasenko <address@hidden>
---
target/sparc/cpu.h | 7 +++----
target/sparc/translate.c | 2 +-
2 files changed, 4 insertions(+), 5 deletions(-)
diff --git a/target/sparc/cpu.h b/target/sparc/cpu.h
index 6c1607e..6fc81e8 100644
--- a/target/sparc/cpu.h
+++ b/target/sparc/cpu.h
@@ -230,7 +230,7 @@ enum {
#if !defined(TARGET_SPARC64)
#define NB_MMU_MODES 3
#else
-#define NB_MMU_MODES 7
+#define NB_MMU_MODES 6
typedef struct trap_state {
uint64_t tpc;
uint64_t tnpc;
@@ -673,8 +673,7 @@ int cpu_sparc_signal_handler(int host_signum, void *pinfo,
void *puc);
#define MMU_KERNEL_IDX 2
#define MMU_KERNEL_SECONDARY_IDX 3
#define MMU_NUCLEUS_IDX 4
-#define MMU_HYPV_IDX 5
-#define MMU_PHYS_IDX 6
+#define MMU_PHYS_IDX 5
#else
#define MMU_USER_IDX 0
#define MMU_KERNEL_IDX 1
@@ -720,7 +719,7 @@ static inline int cpu_mmu_index(CPUSPARCState *env, bool
ifetch)
: (env->lsu & DMMU_E) == 0) {
return MMU_PHYS_IDX;
} else if (cpu_hypervisor_mode(env)) {
- return MMU_HYPV_IDX;
+ return MMU_PHYS_IDX;
} else if (env->tl > 0) {
return MMU_NUCLEUS_IDX;
} else if (cpu_supervisor_mode(env)) {
diff --git a/target/sparc/translate.c b/target/sparc/translate.c
index 23d4673..53c327d 100644
--- a/target/sparc/translate.c
+++ b/target/sparc/translate.c
@@ -2143,7 +2143,7 @@ static DisasASI get_asi(DisasContext *dc, int insn,
TCGMemOp memop)
case ASI_NUCLEUS_QUAD_LDD:
case ASI_NUCLEUS_QUAD_LDD_L:
if (hypervisor(dc)) {
- mem_idx = MMU_HYPV_IDX;
+ mem_idx = MMU_PHYS_IDX;
} else {
mem_idx = MMU_NUCLEUS_IDX;
}
--
1.8.3.1
- [Qemu-devel] [PATCH v2 06/30] target-sparc: on UA2005 don't deliver Interrupt_level_n IRQs in hypervisor mode, (continued)
- [Qemu-devel] [PATCH v2 06/30] target-sparc: on UA2005 don't deliver Interrupt_level_n IRQs in hypervisor mode, Artyom Tarasenko, 2017/01/11
- [Qemu-devel] [PATCH v2 07/30] target-sparc: simplify replace_tlb_entry by using TTE_PGSIZE, Artyom Tarasenko, 2017/01/11
- [Qemu-devel] [PATCH v2 05/30] target-sparc: add UltraSPARC T1 TLB #defines, Artyom Tarasenko, 2017/01/11
- [Qemu-devel] [PATCH v2 08/30] target-sparc: implement UA2005 scratchpad registers, Artyom Tarasenko, 2017/01/11
- [Qemu-devel] [PATCH v2 09/30] target-sparc: implement UltraSPARC-T1 Strand status ASR, Artyom Tarasenko, 2017/01/11
- [Qemu-devel] [PATCH v2 10/30] target-sparc: hypervisor mode takes over nucleus mode, Artyom Tarasenko, 2017/01/11
- [Qemu-devel] [PATCH v2 11/30] target-sparc: implement UA2005 hypervisor traps, Artyom Tarasenko, 2017/01/11
- [Qemu-devel] [PATCH v2 12/30] target-sparc: implement UA2005 GL register, Artyom Tarasenko, 2017/01/11
- [Qemu-devel] [PATCH v2 14/30] target-sparc: fix immediate UA2005 traps, Artyom Tarasenko, 2017/01/11
- [Qemu-devel] [PATCH v2 13/30] target-sparc: implement UA2005 rdhpstate and wrhpstate instructions, Artyom Tarasenko, 2017/01/11
- [Qemu-devel] [PATCH v2 15/30] target-sparc: use direct address translation in hyperprivileged mode,
Artyom Tarasenko <=
- [Qemu-devel] [PATCH v2 17/30] target-sparc: ignore writes to UA2005 CPU mondo queue register, Artyom Tarasenko, 2017/01/11
- [Qemu-devel] [PATCH v2 16/30] target-sparc: allow priveleged ASIs in hyperprivileged mode, Artyom Tarasenko, 2017/01/11
- [Qemu-devel] [PATCH v2 18/30] target-sparc: replace the last tlb entry when no free entries left, Artyom Tarasenko, 2017/01/11
- [Qemu-devel] [PATCH v2 19/30] target-sparc: use SparcV9MMU type for sparc64 I/D-MMUs, Artyom Tarasenko, 2017/01/11
- [Qemu-devel] [PATCH v2 21/30] target-sparc: simplify ultrasparc_tsb_pointer, Artyom Tarasenko, 2017/01/11
- [Qemu-devel] [PATCH v2 20/30] target-sparc: implement UA2005 TSB Pointers, Artyom Tarasenko, 2017/01/11
- [Qemu-devel] [PATCH v2 22/30] target-sparc: allow 256M sized pages, Artyom Tarasenko, 2017/01/11
- [Qemu-devel] [PATCH v2 23/30] target-sparc: implement auto-demapping for UA2005 CPUs, Artyom Tarasenko, 2017/01/11
- [Qemu-devel] [PATCH v2 24/30] target-sparc: add more registers to dump_mmu, Artyom Tarasenko, 2017/01/11
- [Qemu-devel] [PATCH v2 27/30] target-sparc: add ST_BLKINIT_ ASIs for UA2005+ CPUs, Artyom Tarasenko, 2017/01/11