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[Qemu-devel] [PATCH V1 2/4] target-arm: Add support for AArch64 PMU regi
From: |
Wei Huang |
Subject: |
[Qemu-devel] [PATCH V1 2/4] target-arm: Add support for AArch64 PMU register PMXEVTYPER_EL0 |
Date: |
Thu, 12 Jan 2017 02:04:16 -0500 |
In order to support Linux perf, which uses PMXEVTYPER register,
this patch adds access support for PMXEVTYPER_EL0.
Signed-off-by: Wei Huang <address@hidden>
---
target/arm/helper.c | 9 ++++++++-
1 file changed, 8 insertions(+), 1 deletion(-)
diff --git a/target/arm/helper.c b/target/arm/helper.c
index 71adb0f..9044a33 100644
--- a/target/arm/helper.c
+++ b/target/arm/helper.c
@@ -1233,10 +1233,17 @@ static const ARMCPRegInfo v7_cp_reginfo[] = {
.fieldoffset = offsetof(CPUARMState, cp15.pmccfiltr_el0),
.resetvalue = 0, },
{ .name = "PMXEVTYPER", .cp = 15, .crn = 9, .crm = 13, .opc1 = 0, .opc2 =
1,
- .access = PL0_RW,
+ .access = PL0_RW, .type = ARM_CP_ALIAS,
.fieldoffset = offsetof(CPUARMState, cp15.c9_pmxevtyper),
.accessfn = pmreg_access, .writefn = pmxevtyper_write,
.raw_writefn = raw_write },
+ { .name = "PMXEVTYPER_EL0", .state = ARM_CP_STATE_AA64,
+ .opc0 = 3, .opc1 = 3, .crn = 9, .crm = 13, .opc2 = 1,
+ .access = PL0_RW, .accessfn = pmreg_access,
+ .type = ARM_CP_IO,
+ .fieldoffset = offsetof(CPUARMState, cp15.c9_pmxevtyper),
+ .writefn = pmxevtyper_write, .raw_writefn = raw_write,
+ .resetvalue = 0x0 },
/* Unimplemented, RAZ/WI. */
{ .name = "PMXEVCNTR", .cp = 15, .crn = 9, .crm = 13, .opc1 = 0, .opc2 = 2,
.access = PL0_RW, .type = ARM_CP_CONST, .resetvalue = 0,
--
1.8.3.1