[Date Prev][Date Next][Thread Prev][Thread Next][Date Index][Thread Index]
Re: [Qemu-devel] [PATCH 5/5] target-m68k: increment/decrement with SP
From: |
Thomas Huth |
Subject: |
Re: [Qemu-devel] [PATCH 5/5] target-m68k: increment/decrement with SP |
Date: |
Thu, 12 Jan 2017 22:14:19 +0100 |
User-agent: |
Mozilla/5.0 (X11; Linux x86_64; rv:45.0) Gecko/20100101 Thunderbird/45.6.0 |
On 12.01.2017 21:18, Laurent Vivier wrote:
> Address Register indirect With postincrement:
>
> When using the stack pointer (A7) with byte size data, the register
> is incremented by two.
>
> Address Register indirect With predecrement:
>
> When using the stack pointer (A7) with byte size data, the register
> is decremented by two.
I think this is only valid for the full 680x0 CPUs. According to
http://www.nxp.com/assets/documents/data/en/reference-manuals/CFPRM.pdf
the stack pointer behaves differently on ColdFire:
"2.2.5 Address Register Indirect with Predecrement Mode [...]
Note that the stack pointer (A7) is treated just like the other address
registers."
Thomas
- [Qemu-devel] [PATCH 0/5] Fixes for target/m68k, Laurent Vivier, 2017/01/12
- [Qemu-devel] [PATCH 1/5] target-m68k: fix bit operation with immediate value, Laurent Vivier, 2017/01/12
- [Qemu-devel] [PATCH 4/5] target-m68k: CAS doesn't need aligned access, Laurent Vivier, 2017/01/12
- [Qemu-devel] [PATCH 3/5] target-m68k: manage pre-dec et post-inc in CAS, Laurent Vivier, 2017/01/12
- [Qemu-devel] [PATCH 5/5] target-m68k: increment/decrement with SP, Laurent Vivier, 2017/01/12
- Re: [Qemu-devel] [PATCH 5/5] target-m68k: increment/decrement with SP,
Thomas Huth <=
- [Qemu-devel] [PATCH 2/5] target-m68k: fix gen_flush_flags(), Laurent Vivier, 2017/01/12