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Re: [Qemu-devel] [PATCH 2/3] target/arm: Handle VIRQ and VFIQ in arm_cpu
From: |
Edgar E. Iglesias |
Subject: |
Re: [Qemu-devel] [PATCH 2/3] target/arm: Handle VIRQ and VFIQ in arm_cpu_do_interrupt_aarch32() |
Date: |
Thu, 12 Jan 2017 22:41:52 +0100 |
User-agent: |
Mutt/1.5.24 (2015-08-30) |
On Tue, Jan 10, 2017 at 06:44:08PM +0000, Peter Maydell wrote:
> To run a VM in 32-bit EL1 our AArch32 interrupt handling code
> needs to be able to cope with VIRQ and VFIQ exceptions.
> These behave like IRQ and FIQ except that we don't need to try
> to route them to Monitor mode.
>
> Signed-off-by: Peter Maydell <address@hidden>
We could possibly avoid some duplication with EXCP_IRQ and _FIQ
but either way works:
Reviewed-by: Edgar E. Iglesias <address@hidden>
> ---
> target/arm/helper.c | 14 ++++++++++++++
> 1 file changed, 14 insertions(+)
>
> diff --git a/target/arm/helper.c b/target/arm/helper.c
> index 8dcabbf..dc90986 100644
> --- a/target/arm/helper.c
> +++ b/target/arm/helper.c
> @@ -6403,6 +6403,20 @@ static void arm_cpu_do_interrupt_aarch32(CPUState *cs)
> }
> offset = 4;
> break;
> + case EXCP_VIRQ:
> + new_mode = ARM_CPU_MODE_IRQ;
> + addr = 0x18;
> + /* Disable IRQ and imprecise data aborts. */
> + mask = CPSR_A | CPSR_I;
> + offset = 4;
> + break;
> + case EXCP_VFIQ:
> + new_mode = ARM_CPU_MODE_FIQ;
> + addr = 0x1c;
> + /* Disable FIQ, IRQ and imprecise data aborts. */
> + mask = CPSR_A | CPSR_I | CPSR_F;
> + offset = 4;
> + break;
> case EXCP_SMC:
> new_mode = ARM_CPU_MODE_MON;
> addr = 0x08;
> --
> 2.7.4
>
- [Qemu-devel] [PATCH 0/3] target/arm: Support EL1 AArch32 guest under AArch64 EL2, Peter Maydell, 2017/01/10
- [Qemu-devel] [PATCH 3/3] target/arm: Implement DBGVCR32_EL2 system register, Peter Maydell, 2017/01/10
- [Qemu-devel] [PATCH 2/3] target/arm: Handle VIRQ and VFIQ in arm_cpu_do_interrupt_aarch32(), Peter Maydell, 2017/01/10
- Re: [Qemu-devel] [PATCH 2/3] target/arm: Handle VIRQ and VFIQ in arm_cpu_do_interrupt_aarch32(),
Edgar E. Iglesias <=
- [Qemu-devel] [PATCH 1/3] target/arm: A32, T32: Create Instruction Syndromes for Data Aborts, Peter Maydell, 2017/01/10
- Re: [Qemu-devel] [PATCH 0/3] target/arm: Support EL1 AArch32 guest under AArch64 EL2, Edgar E. Iglesias, 2017/01/12