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[Qemu-devel] [PATCH v3 2/7] Honour reset_sctlr EE/B bits during reset.


From: Julian Brown
Subject: [Qemu-devel] [PATCH v3 2/7] Honour reset_sctlr EE/B bits during reset.
Date: Fri, 20 Jan 2017 08:30:27 -0800

This patch uses the reset value of the SCTLR register (e.g. as modified
by the "cfgend" parameter introduced by the previous patch) to set the
endianness used by QEMU when it is invoked without a kernel or firmware
image. The intended use case is loading code via GDB as follows:

  (gdb) target remote | qemu-arm-system [options] -cpu=cortex-a15,cfgend=yes
  (gdb) load
  (gdb) [...]

The idea being to start a board in a "reset" state in the selected
endianness so that communication with GDB works properly. (The previous
version of the patch used "-kernel /dev/null" for the same purpose:
this version avoids that, and also avoids fiddling with info->endianness
setting.)

Signed-off-by: Julian Brown <address@hidden>
---
 hw/arm/boot.c | 27 +++++++++++++++++++++++++++
 1 file changed, 27 insertions(+)

diff --git a/hw/arm/boot.c b/hw/arm/boot.c
index ff621e4..c059bd2 100644
--- a/hw/arm/boot.c
+++ b/hw/arm/boot.c
@@ -646,6 +646,33 @@ static void do_cpu_reset(void *opaque)
                 info->secondary_cpu_reset_hook(cpu, info);
             }
         }
+    } else {
+       /* No kernel image or firmware has been supplied.  Reset to the
+        * default endianness for the current board (e.g. so that code loaded
+        * via the gdb stub interface does the right thing).
+        */
+       if (arm_feature(env, ARM_FEATURE_V7)) {
+           int i;
+           if (cpu->reset_sctlr & SCTLR_EE) {
+               env->cp15.sctlr_el[1] |= SCTLR_E0E;
+               for (i = 1; i < 4; ++i) {
+                   env->cp15.sctlr_el[i] |= SCTLR_EE;
+               }
+               env->uncached_cpsr |= CPSR_E;
+           } else {
+                env->cp15.sctlr_el[1] &= ~SCTLR_E0E;
+                for (i = 1; i < 4; ++i) {
+                    env->cp15.sctlr_el[i] &= ~SCTLR_EE;
+                }
+                env->uncached_cpsr &= ~CPSR_E;
+           }
+       } else {
+           if (cpu->reset_sctlr & SCTLR_B) {
+               env->cp15.sctlr_el[1] |= SCTLR_B;
+           } else {
+               env->cp15.sctlr_el[1] &= ~SCTLR_B;
+           }
+       }
     }
 }
 
-- 
2.8.1




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