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[Qemu-devel] [PATCH 05/10] armv7m: honour CCR.STACKALIGN on exception en
From: |
Peter Maydell |
Subject: |
[Qemu-devel] [PATCH 05/10] armv7m: honour CCR.STACKALIGN on exception entry |
Date: |
Tue, 24 Jan 2017 19:16:15 +0000 |
From: Michael Davidsaver <address@hidden>
The CCR.STACKALIGN bit controls whether the CPU is supposed to force
8-alignment of the stack pointer on entry to the exception handler.
Signed-off-by: Michael Davidsaver <address@hidden>
[PMM: commit message and comment tweaks]
Signed-off-by: Peter Maydell <address@hidden>
---
target/arm/helper.c | 6 ++----
1 file changed, 2 insertions(+), 4 deletions(-)
diff --git a/target/arm/helper.c b/target/arm/helper.c
index ce7e43b..7dc30f5 100644
--- a/target/arm/helper.c
+++ b/target/arm/helper.c
@@ -6110,10 +6110,8 @@ void arm_v7m_cpu_do_interrupt(CPUState *cs)
return; /* Never happens. Keep compiler happy. */
}
- /* Align stack pointer. */
- /* ??? Should only do this if Configuration Control Register
- STACKALIGN bit is set. */
- if (env->regs[13] & 4) {
+ /* Align stack pointer if the guest wants that */
+ if ((env->regs[13] & 4) && (env->v7m.ccr & R_V7M_CCR_STKALIGN_MASK)) {
env->regs[13] -= 4;
xpsr |= 0x200;
}
--
2.7.4
- [Qemu-devel] [PATCH 10/10] armv7m: R14 should reset to 0xffffffff, (continued)
- [Qemu-devel] [PATCH 10/10] armv7m: R14 should reset to 0xffffffff, Peter Maydell, 2017/01/24
- [Qemu-devel] [PATCH 08/10] armv7m: Honour CCR.USERSETMPEND, Peter Maydell, 2017/01/24
- [Qemu-devel] [PATCH 04/10] armv7m: implement CCR, CFSR, HFSR, DFSR, BFAR, and MMFAR, Peter Maydell, 2017/01/24
- [Qemu-devel] [PATCH 02/10] armv7m_nvic: keep a pointer to the CPU, Peter Maydell, 2017/01/24
- [Qemu-devel] [PATCH 03/10] armv7m: add state for v7M CCR, CFSR, HFSR, DFSR, MMFAR, BFAR, Peter Maydell, 2017/01/24
- [Qemu-devel] [PATCH 05/10] armv7m: honour CCR.STACKALIGN on exception entry,
Peter Maydell <=
- [Qemu-devel] [PATCH 06/10] armv7m: set CFSR.UNDEFINSTR on undefined instructions, Peter Maydell, 2017/01/24
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