[Qemu-devel] [RFC PATCH v2 0/2] softfloat: Add round-to-odd rounding mode

[Bharata B Rao]

Hi,

Here is the next version of round-to-odd rounding mode implementation.

In this version I have addressed the reveiw comments from v1 and added
a new patch to take care of 64 bit rounding in underflow case. This
fix was found necessary when comparing the result of PowerPC ISA 3.0
instruction xscvqpdp between QEMU implementation and a known-good
implementation.

I have tested these patches and compared the results of
xsaddqp[o], xsmulqp[o], xsdivqp[o] and xscvqpdp[0] between QEMU
implementation and a known-good implementation.

I wanted to test with RISU to check if any older floating point
instructions (prior to PowerPC ISA v3.0) were affected by these
rounding changes. But even without my patchset, I am seeing RISU
reporting failures between QEMU implementation and P8 hardware.
While I am investigating the cause for these failures, I also plan
to do RISU verification for ISA 3.0 instructions with a known good
implementation.

Changes in v2:
-------------
- Do odd or even for the right precision bit in 64bit rounding. (Peter Maydell)
- Handle the overflow case correctly in 64bit rounding. (Peter Maydell)
- Add a patch to handle underflow case correctly in 64bit rounding.
 
v1: http://patchwork.ozlabs.org/patch/717562/

Bharata B Rao (2):
  softfloat: Handle float64 rounding properly for underflow case
  softfloat: Add round-to-odd rounding mode

 fpu/softfloat.c         | 34 +++++++++++++++++++++++++++++++++-
 include/fpu/softfloat.h |  2 ++
 2 files changed, 35 insertions(+), 1 deletion(-)

-- 
2.7.4