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[Qemu-devel] [PULL 04/22] armv7m: Explicit error for bad vector table
From: |
Peter Maydell |
Subject: |
[Qemu-devel] [PULL 04/22] armv7m: Explicit error for bad vector table |
Date: |
Fri, 27 Jan 2017 15:31:59 +0000 |
From: Michael Davidsaver <address@hidden>
Give an explicit error and abort when a load
from the vector table fails. Architecturally this
should HardFault (which will then immediately
fail to load the HardFault vector and go into Lockup).
Since we don't model Lockup, just report this guest
error via cpu_abort(). This is more helpful than the
previous behaviour of reading a zero, which is the
address of the reset stack pointer and not a sensible
location to jump to.
Signed-off-by: Michael Davidsaver <address@hidden>
Reviewed-by: Peter Maydell <address@hidden>
Reviewed-by: Alex Bennée <address@hidden>
Message-id: address@hidden
[PMM: expanded commit message]
Signed-off-by: Peter Maydell <address@hidden>
---
target/arm/helper.c | 26 +++++++++++++++++++++++++-
1 file changed, 25 insertions(+), 1 deletion(-)
diff --git a/target/arm/helper.c b/target/arm/helper.c
index ad23de3..8edb08c 100644
--- a/target/arm/helper.c
+++ b/target/arm/helper.c
@@ -6014,6 +6014,30 @@ static void arm_log_exception(int idx)
}
}
+static uint32_t arm_v7m_load_vector(ARMCPU *cpu)
+
+{
+ CPUState *cs = CPU(cpu);
+ CPUARMState *env = &cpu->env;
+ MemTxResult result;
+ hwaddr vec = env->v7m.vecbase + env->v7m.exception * 4;
+ uint32_t addr;
+
+ addr = address_space_ldl(cs->as, vec,
+ MEMTXATTRS_UNSPECIFIED, &result);
+ if (result != MEMTX_OK) {
+ /* Architecturally this should cause a HardFault setting HSFR.VECTTBL,
+ * which would then be immediately followed by our failing to load
+ * the entry vector for that HardFault, which is a Lockup case.
+ * Since we don't model Lockup, we just report this guest error
+ * via cpu_abort().
+ */
+ cpu_abort(cs, "Failed to read from exception vector table "
+ "entry %08x\n", (unsigned)vec);
+ }
+ return addr;
+}
+
void arm_v7m_cpu_do_interrupt(CPUState *cs)
{
ARMCPU *cpu = ARM_CPU(cs);
@@ -6095,7 +6119,7 @@ void arm_v7m_cpu_do_interrupt(CPUState *cs)
/* Clear IT bits */
env->condexec_bits = 0;
env->regs[14] = lr;
- addr = ldl_phys(cs->as, env->v7m.vecbase + env->v7m.exception * 4);
+ addr = arm_v7m_load_vector(cpu);
env->regs[15] = addr & 0xfffffffe;
env->thumb = addr & 1;
}
--
2.7.4
- [Qemu-devel] [PULL 14/22] armv7m: set CFSR.UNDEFINSTR on undefined instructions, (continued)
- [Qemu-devel] [PULL 14/22] armv7m: set CFSR.UNDEFINSTR on undefined instructions, Peter Maydell, 2017/01/27
- [Qemu-devel] [PULL 13/22] armv7m: honour CCR.STACKALIGN on exception entry, Peter Maydell, 2017/01/27
- [Qemu-devel] [PULL 09/22] target/arm: Drop IS_M() macro, Peter Maydell, 2017/01/27
- [Qemu-devel] [PULL 16/22] armv7m: Honour CCR.USERSETMPEND, Peter Maydell, 2017/01/27
- [Qemu-devel] [PULL 05/22] hw/registerfields.h: Pull FIELD etc macros out of hw/register.h, Peter Maydell, 2017/01/27
- [Qemu-devel] [PULL 07/22] armv7m: Clear FAULTMASK on return from non-NMI exceptions, Peter Maydell, 2017/01/27
- [Qemu-devel] [PULL 01/22] aspeed/smc: handle dummy bytes when doing fast reads in command mode, Peter Maydell, 2017/01/27
- [Qemu-devel] [PULL 02/22] armv7m: MRS/MSR: handle unprivileged access, Peter Maydell, 2017/01/27
- [Qemu-devel] [PULL 12/22] armv7m: implement CCR, CFSR, HFSR, DFSR, BFAR, and MMFAR, Peter Maydell, 2017/01/27
- [Qemu-devel] [PULL 06/22] armv7m: Fix reads of CONTROL register bit 1, Peter Maydell, 2017/01/27
- [Qemu-devel] [PULL 04/22] armv7m: Explicit error for bad vector table,
Peter Maydell <=
- [Qemu-devel] [PULL 11/22] armv7m: add state for v7M CCR, CFSR, HFSR, DFSR, MMFAR, BFAR, Peter Maydell, 2017/01/27
- [Qemu-devel] [PULL 10/22] armv7m_nvic: keep a pointer to the CPU, Peter Maydell, 2017/01/27
- [Qemu-devel] [PULL 08/22] pflash_cfi01: fix per-device sector length in CFI table, Peter Maydell, 2017/01/27
- [Qemu-devel] [PULL 15/22] armv7m: Report no-coprocessor faults correctly, Peter Maydell, 2017/01/27
- [Qemu-devel] [PULL 03/22] armv7m: Replace armv7m.hack with unassigned_access handler, Peter Maydell, 2017/01/27
- Re: [Qemu-devel] [PULL 00/22] target-arm queue, no-reply, 2017/01/27
- Re: [Qemu-devel] [PULL 00/22] target-arm queue, Peter Maydell, 2017/01/30
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