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[Qemu-devel] [PULL 058/107] target-ppc: Add xsxsigdp instruction
From: |
David Gibson |
Subject: |
[Qemu-devel] [PULL 058/107] target-ppc: Add xsxsigdp instruction |
Date: |
Thu, 2 Feb 2017 16:13:56 +1100 |
From: Nikunj A Dadhania <address@hidden>
xsxsigdp: VSX Scalar Extract Significand Dual Precision
Signed-off-by: Nikunj A Dadhania <address@hidden>
Signed-off-by: David Gibson <address@hidden>
---
target/ppc/translate/vsx-impl.inc.c | 29 +++++++++++++++++++++++++++++
target/ppc/translate/vsx-ops.inc.c | 1 +
2 files changed, 30 insertions(+)
diff --git a/target/ppc/translate/vsx-impl.inc.c
b/target/ppc/translate/vsx-impl.inc.c
index 228e2a5..c6f2208 100644
--- a/target/ppc/translate/vsx-impl.inc.c
+++ b/target/ppc/translate/vsx-impl.inc.c
@@ -1239,6 +1239,35 @@ static void gen_xsxexpqp(DisasContext *ctx)
tcg_gen_andi_i64(xth, xth, 0x7FFF);
tcg_gen_movi_i64(xtl, 0);
}
+
+static void gen_xsxsigdp(DisasContext *ctx)
+{
+ TCGv rt = cpu_gpr[rD(ctx->opcode)];
+ TCGv_i64 t0, zr, nan, exp;
+
+ if (unlikely(!ctx->vsx_enabled)) {
+ gen_exception(ctx, POWERPC_EXCP_VSXU);
+ return;
+ }
+ exp = tcg_temp_new_i64();
+ t0 = tcg_temp_new_i64();
+ zr = tcg_const_i64(0);
+ nan = tcg_const_i64(2047);
+
+ tcg_gen_shri_i64(exp, cpu_vsrh(xB(ctx->opcode)), 52);
+ tcg_gen_andi_i64(exp, exp, 0x7FF);
+ tcg_gen_movi_i64(t0, 0x0010000000000000);
+ tcg_gen_movcond_i64(TCG_COND_EQ, t0, exp, zr, zr, t0);
+ tcg_gen_movcond_i64(TCG_COND_EQ, t0, exp, nan, zr, t0);
+ tcg_gen_andi_i64(rt, cpu_vsrh(xB(ctx->opcode)), 0x000FFFFFFFFFFFFF);
+ tcg_gen_or_i64(rt, rt, t0);
+
+ tcg_temp_free_i64(t0);
+ tcg_temp_free_i64(exp);
+ tcg_temp_free_i64(zr);
+ tcg_temp_free_i64(nan);
+}
+
#endif
#undef GEN_XX2FORM
diff --git a/target/ppc/translate/vsx-ops.inc.c
b/target/ppc/translate/vsx-ops.inc.c
index 87f1852..1fd5285 100644
--- a/target/ppc/translate/vsx-ops.inc.c
+++ b/target/ppc/translate/vsx-ops.inc.c
@@ -116,6 +116,7 @@ GEN_VSX_XFORM_300(xscpsgnqp, 0x04, 0x03, 0x00000001),
#ifdef TARGET_PPC64
GEN_XX2FORM_EO(xsxexpdp, 0x16, 0x15, 0x00, PPC2_ISA300),
GEN_VSX_XFORM_300_EO(xsxexpqp, 0x04, 0x19, 0x02, 0x00000001),
+GEN_XX2FORM_EO(xsxsigdp, 0x16, 0x15, 0x01, PPC2_ISA300),
#endif
GEN_XX2FORM(xvabsdp, 0x12, 0x1D, PPC2_VSX),
--
2.9.3
- [Qemu-devel] [PULL 069/107] softfloat: Fix the default qNAN for target-ppc, (continued)
- [Qemu-devel] [PULL 069/107] softfloat: Fix the default qNAN for target-ppc, David Gibson, 2017/02/02
- [Qemu-devel] [PULL 087/107] target-ppc: Use ppc_vsr_t.f128 in xscmp[o, u, exp]qp, David Gibson, 2017/02/02
- [Qemu-devel] [PULL 071/107] host-utils: Implement unsigned quadword left/right shift and unit tests, David Gibson, 2017/02/02
- [Qemu-devel] [PULL 059/107] target-ppc: Add xsxsigqp instructions, David Gibson, 2017/02/02
- [Qemu-devel] [PULL 050/107] prep: add IBM RS/6000 7020 (40p) machine emulation, David Gibson, 2017/02/02
- [Qemu-devel] [PULL 070/107] host-utils: Move 128-bit guard macro to .c file, David Gibson, 2017/02/02
- [Qemu-devel] [PULL 100/107] target-ppc: Add xvtstdc[sp, dp] instructions, David Gibson, 2017/02/02
- [Qemu-devel] [PULL 077/107] target-ppc: Add xviexpsp instruction, David Gibson, 2017/02/02
- [Qemu-devel] [PULL 058/107] target-ppc: Add xsxsigdp instruction,
David Gibson <=
- [Qemu-devel] [PULL 060/107] pxb: Restrict to x86, David Gibson, 2017/02/02
- [Qemu-devel] [PULL 072/107] ppc: Implement bcds. instruction, David Gibson, 2017/02/02
- [Qemu-devel] [PULL 062/107] ppc: Add ppc_set_compat_all(), David Gibson, 2017/02/02
- [Qemu-devel] [PULL 075/107] target-ppc: Add xsiexpdp instruction, David Gibson, 2017/02/02
- [Qemu-devel] [PULL 053/107] target-ppc: Rename helper_compute_fprf to helper_compute_fprf_float64, David Gibson, 2017/02/02
- [Qemu-devel] [PULL 099/107] target-ppc: Add MMU model check for booke machines, David Gibson, 2017/02/02
- [Qemu-devel] [PULL 097/107] target/ppc/cpu-models: Fix/remove bad CPU aliases, David Gibson, 2017/02/02
- [Qemu-devel] [PULL 081/107] target-ppc: Add xvxsigsp instruction, David Gibson, 2017/02/02
- [Qemu-devel] [PULL 074/107] ppc: Implement bcdsr. instruction, David Gibson, 2017/02/02
- [Qemu-devel] [PULL 082/107] target-ppc: Add xvxsigdp instruction, David Gibson, 2017/02/02