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[Qemu-devel] [PULL 093/107] target/ppc: Add pcr_supported to POWER9 cpu
From: |
David Gibson |
Subject: |
[Qemu-devel] [PULL 093/107] target/ppc: Add pcr_supported to POWER9 cpu class definition |
Date: |
Thu, 2 Feb 2017 16:14:31 +1100 |
From: Suraj Jitindar Singh <address@hidden>
pcr_supported is used to define the supported PCR values for a given
processor. A POWER9 processor can support 3.00, 2.07, 2.06 and 2.05
compatibility modes, thus we set this accordingly.
Signed-off-by: Suraj Jitindar Singh <address@hidden>
Signed-off-by: David Gibson <address@hidden>
---
target/ppc/cpu.h | 1 +
target/ppc/translate_init.c | 2 ++
2 files changed, 3 insertions(+)
diff --git a/target/ppc/cpu.h b/target/ppc/cpu.h
index 4d72d75..bc2a2ce 100644
--- a/target/ppc/cpu.h
+++ b/target/ppc/cpu.h
@@ -2290,6 +2290,7 @@ enum {
PCR_COMPAT_2_05 = 1ull << (63-62),
PCR_COMPAT_2_06 = 1ull << (63-61),
PCR_COMPAT_2_07 = 1ull << (63-60),
+ PCR_COMPAT_3_00 = 1ull << (63-59),
PCR_VEC_DIS = 1ull << (63-0), /* Vec. disable (bit NA since
POWER8) */
PCR_VSX_DIS = 1ull << (63-1), /* VSX disable (bit NA since POWER8)
*/
PCR_TM_DIS = 1ull << (63-2), /* Trans. memory disable (POWER8) */
diff --git a/target/ppc/translate_init.c b/target/ppc/translate_init.c
index 388a3e8..c7f7624 100644
--- a/target/ppc/translate_init.c
+++ b/target/ppc/translate_init.c
@@ -8797,6 +8797,8 @@ POWERPC_FAMILY(POWER9)(ObjectClass *oc, void *data)
dc->props = powerpc_servercpu_properties;
pcc->pvr_match = ppc_pvr_match_power9;
pcc->pcr_mask = PCR_COMPAT_2_05 | PCR_COMPAT_2_06 | PCR_COMPAT_2_07;
+ pcc->pcr_supported = PCR_COMPAT_3_00 | PCR_COMPAT_2_07 | PCR_COMPAT_2_06 |
+ PCR_COMPAT_2_05;
pcc->init_proc = init_proc_POWER9;
pcc->check_pow = check_pow_nocheck;
pcc->insns_flags = PPC_INSNS_BASE | PPC_ISEL | PPC_STRING | PPC_MFTB |
--
2.9.3
- [Qemu-devel] [PULL 075/107] target-ppc: Add xsiexpdp instruction, (continued)
- [Qemu-devel] [PULL 075/107] target-ppc: Add xsiexpdp instruction, David Gibson, 2017/02/02
- [Qemu-devel] [PULL 053/107] target-ppc: Rename helper_compute_fprf to helper_compute_fprf_float64, David Gibson, 2017/02/02
- [Qemu-devel] [PULL 099/107] target-ppc: Add MMU model check for booke machines, David Gibson, 2017/02/02
- [Qemu-devel] [PULL 097/107] target/ppc/cpu-models: Fix/remove bad CPU aliases, David Gibson, 2017/02/02
- [Qemu-devel] [PULL 081/107] target-ppc: Add xvxsigsp instruction, David Gibson, 2017/02/02
- [Qemu-devel] [PULL 074/107] ppc: Implement bcdsr. instruction, David Gibson, 2017/02/02
- [Qemu-devel] [PULL 082/107] target-ppc: Add xvxsigdp instruction, David Gibson, 2017/02/02
- [Qemu-devel] [PULL 080/107] target-ppc: Add xvxexpdp instruction, David Gibson, 2017/02/02
- [Qemu-devel] [PULL 094/107] ppc: Remove unused function cpu_ppc601_rtc_init(), David Gibson, 2017/02/02
- [Qemu-devel] [PULL 079/107] target-ppc: Add xvxexpsp instruction, David Gibson, 2017/02/02
- [Qemu-devel] [PULL 093/107] target/ppc: Add pcr_supported to POWER9 cpu class definition,
David Gibson <=
- [Qemu-devel] [PULL 098/107] ppc: switch to constants within BUILD_BUG_ON, David Gibson, 2017/02/02
- [Qemu-devel] [PULL 085/107] ppc: Implement bcdtrunc. instruction, David Gibson, 2017/02/02
- [Qemu-devel] [PULL 086/107] ppc: Implement bcdutrunc. instruction, David Gibson, 2017/02/02
- [Qemu-devel] [PULL 089/107] target-ppc: Add xsdivqp instruction, David Gibson, 2017/02/02
- [Qemu-devel] [PULL 101/107] target-ppc: Add xststdc[sp, dp, qp] instructions, David Gibson, 2017/02/02
- [Qemu-devel] [PULL 084/107] ppc/prep: update MAINTAINERS file, David Gibson, 2017/02/02
- [Qemu-devel] [PULL 088/107] target-ppc: Add xscvsdqp and xscvudqp instructions, David Gibson, 2017/02/02
- [Qemu-devel] [PULL 102/107] target/ppc/debug: Print LPCR register value if register exists, David Gibson, 2017/02/02
- [Qemu-devel] [PULL 091/107] target-ppc: Add xvcv[hpsp, sphp] instructions, David Gibson, 2017/02/02
- [Qemu-devel] [PULL 083/107] target-ppc: Add xscvqps[d, w]z instructions, David Gibson, 2017/02/02