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[Qemu-devel] [PATCH v3 2/4] sd: sdhci: mask transfer mode register value
From: |
P J P |
Subject: |
[Qemu-devel] [PATCH v3 2/4] sd: sdhci: mask transfer mode register value |
Date: |
Sat, 11 Feb 2017 20:36:59 +0530 |
From: Prasad J Pandit <address@hidden>
In SDHCI protocol, the transfer mode register is defined
to be of 6 bits. Mask its value with '0x0037' so that an
invalid value couldn't be assigned.
Signed-off-by: Prasad J Pandit <address@hidden>
---
hw/sd/sdhci.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
Update: mask s->trnmod register value
-> https://lists.gnu.org/archive/html/qemu-devel/2017-02/msg02354.html
diff --git a/hw/sd/sdhci.c b/hw/sd/sdhci.c
index a9c744b..0307b8c 100644
--- a/hw/sd/sdhci.c
+++ b/hw/sd/sdhci.c
@@ -1050,7 +1050,7 @@ sdhci_write(void *opaque, hwaddr offset, uint64_t val,
unsigned size)
if (!(s->capareg & SDHC_CAN_DO_DMA)) {
value &= ~SDHC_TRNS_DMA;
}
- MASKED_WRITE(s->trnmod, mask, value);
+ MASKED_WRITE(s->trnmod, mask, value & 0x0037);
MASKED_WRITE(s->cmdreg, mask >> 16, value >> 16);
/* Writing to the upper byte of CMDREG triggers SD command generation
*/
--
2.9.3