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[Qemu-devel] [PULL 05/24] target/openrisc: Fix exception handling status
From: |
Richard Henderson |
Subject: |
[Qemu-devel] [PULL 05/24] target/openrisc: Fix exception handling status registers |
Date: |
Tue, 14 Feb 2017 08:25:17 +1100 |
From: Stafford Horne <address@hidden>
I am working on testing instruction emulation patches for the linux
kernel. During testing I found these 2 issues:
- sets DSX (delay slot exception) but never clears it
- EEAR for illegal insns should point to the bad exception (as per
openrisc spec) but its not
This patch fixes these two issues by clearing the DSX flag when not in a
delay slot and by setting EEAR to exception PC when handling illegal
instruction exceptions.
After this patch the openrisc kernel with latest patches boots great on
qemu and instruction emulation works.
Cc: address@hidden
Cc: address@hidden
Signed-off-by: Stafford Horne <address@hidden>
Message-Id: <address@hidden>
Signed-off-by: Richard Henderson <address@hidden>
---
target/openrisc/interrupt.c | 7 +++++++
1 file changed, 7 insertions(+)
diff --git a/target/openrisc/interrupt.c b/target/openrisc/interrupt.c
index e43fc84..a243eb2 100644
--- a/target/openrisc/interrupt.c
+++ b/target/openrisc/interrupt.c
@@ -38,10 +38,17 @@ void openrisc_cpu_do_interrupt(CPUState *cs)
env->flags &= ~D_FLAG;
env->sr |= SR_DSX;
env->epcr -= 4;
+ } else {
+ env->sr &= ~SR_DSX;
}
if (cs->exception_index == EXCP_SYSCALL) {
env->epcr += 4;
}
+ /* When we have an illegal instruction the error effective address
+ shall be set to the illegal instruction address. */
+ if (cs->exception_index == EXCP_ILLEGAL) {
+ env->eear = env->pc;
+ }
/* For machine-state changed between user-mode and supervisor mode,
we need flush TLB when we enter&exit EXCP. */
--
2.9.3
- [Qemu-devel] [PULL 00/24] target/openrisc patches, Richard Henderson, 2017/02/13
- [Qemu-devel] [PULL 01/24] target/openrisc: Rename the cpu from or32 to or1k, Richard Henderson, 2017/02/13
- [Qemu-devel] [PULL 03/24] linux-user: Fix openrisc cpu_loop, Richard Henderson, 2017/02/13
- [Qemu-devel] [PULL 04/24] linux-user: Honor CLONE_SETTLS for openrisc, Richard Henderson, 2017/02/13
- [Qemu-devel] [PULL 05/24] target/openrisc: Fix exception handling status registers,
Richard Henderson <=
- [Qemu-devel] [PULL 07/24] target/openrisc: Tidy insn dumping, Richard Henderson, 2017/02/13
- [Qemu-devel] [PULL 06/24] target/openrisc: Implement lwa, swa, Richard Henderson, 2017/02/13
- [Qemu-devel] [PULL 08/24] target/openrisc: Rationalize immediate extraction, Richard Henderson, 2017/02/13
- [Qemu-devel] [PULL 10/24] target/openrisc: Put SR[OVE] in TB flags, Richard Henderson, 2017/02/13
- [Qemu-devel] [PULL 11/24] target/openrisc: Invert the decoding in dec_calc, Richard Henderson, 2017/02/13
- [Qemu-devel] [PULL 09/24] target/openrisc: Streamline arithmetic and OVE, Richard Henderson, 2017/02/13
- [Qemu-devel] [PULL 12/24] target/openrisc: Keep SR_F in a separate variable, Richard Henderson, 2017/02/13
- [Qemu-devel] [PULL 14/24] target/openrisc: Use movcond where appropriate, Richard Henderson, 2017/02/13
- [Qemu-devel] [PULL 13/24] target/openrisc: Keep SR_CY and SR_OV in a separate variables, Richard Henderson, 2017/02/13
- [Qemu-devel] [PULL 16/24] target/openrisc: Enable trap, csync, msync, psync for user mode, Richard Henderson, 2017/02/13