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Re: [Qemu-devel] [Qemu-ppc] [QEMU-PPC] [PATCH V3 02/10] target/ppc: Fix
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From: |
Balbir Singh |
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Subject: |
Re: [Qemu-devel] [Qemu-ppc] [QEMU-PPC] [PATCH V3 02/10] target/ppc: Fix LPCR DPFD mask define |
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Date: |
Mon, 20 Feb 2017 16:47:56 +1100 |
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User-agent: |
Mutt/1.7.1 (2016-10-04) |
On Mon, Feb 20, 2017 at 03:04:30PM +1100, Suraj Jitindar Singh wrote:
> The DPFD field in the LPCR is 3 bits wide. This has always been defined
> as 0x3 << shift which indicates a 2 bit field, which is incorrect.
> Correct this.
>
> Signed-off-by: Suraj Jitindar Singh <address@hidden>
> ---
Acked-by: Balbir Singh <address@hidden>
[Qemu-devel] [QEMU-PPC] [PATCH V3 04/10] target/ppc/POWER9: Direct all instr and data storage interrupts to the hypv, Suraj Jitindar Singh, 2017/02/19
[Qemu-devel] [QEMU-PPC] [PATCH V3 05/10] target/ppc: Add patb_entry to sPAPRMachineState, Suraj Jitindar Singh, 2017/02/19