[Date Prev][Date Next][Thread Prev][Thread Next][Date Index][Thread Index]
Re: [Qemu-devel] [PATCH v3 00/10] POWER9 TCG enablements - part15
From: |
David Gibson |
Subject: |
Re: [Qemu-devel] [PATCH v3 00/10] POWER9 TCG enablements - part15 |
Date: |
Thu, 23 Feb 2017 14:27:49 +1100 |
User-agent: |
Mutt/1.7.1 (2016-10-04) |
On Wed, Feb 22, 2017 at 05:14:33PM +0530, Nikunj A Dadhania wrote:
> This series contains implentation of CA32 and OV32 bits added to the
> ISA 3.0. Various fixed-point arithmetic instructions are updated to take
> care of the newer flags.
>
> Finally the last patch adds new instruction mcrxrx, that helps reading
> the carry (CA and CA32) and the overflow (OV and OV32) flags
I've applied patches 1 & 2 to ppc-for-2.9.
The rest I've left for a resend pending my comments and rth's.
>
> Changelog:
> v2:
> * Add missing condition in narrow mode(add/subf), multiply and divide
> * Drop nego patch, subf implementation is sufficient for setting OV and OV32
> * Retaining neg[.], as the code is simplified.
> * Fix OV resetting in compute_ov()
>
> v1:
> * Use these ISA 3.0 flag to enable CA32 and OV32
> * Re-write ca32 compute routine
> * Add setting of flags for "neg." and "nego."
>
> Nikunj A Dadhania (10):
> target/ppc: move cpu_[read, write]_xer to cpu.c
> target/ppc: optimize gen_write_xer()
> target/ppc: support for 32-bit carry and overflow
> target/ppc: update ca32 in arithmetic add
> target/ppc: update ca32 in arithmetic substract
> target/ppc: update overflow flags for add/sub
> target/ppc: use tcg ops for neg instruction
> target/ppc: add ov32 flag for multiply low insns
> target/ppc: add ov32 flag in divide operations
> target/ppc: add mcrxrx instruction
>
> target/ppc/Makefile.objs | 1 +
> target/ppc/cpu.c | 51 ++++++++++++++++++
> target/ppc/cpu.h | 21 ++++----
> target/ppc/int_helper.c | 53 +++++++-----------
> target/ppc/translate.c | 128
> ++++++++++++++++++++++++++++++++++++++------
> target/ppc/translate_init.c | 4 +-
> 6 files changed, 194 insertions(+), 64 deletions(-)
> create mode 100644 target/ppc/cpu.c
>
--
David Gibson | I'll have my music baroque, and my code
david AT gibson.dropbear.id.au | minimalist, thank you. NOT _the_ _other_
| _way_ _around_!
http://www.ozlabs.org/~dgibson
signature.asc
Description: PGP signature
- [Qemu-devel] [PATCH v3 05/10] target/ppc: update ca32 in arithmetic substract, (continued)
- [Qemu-devel] [PATCH v3 05/10] target/ppc: update ca32 in arithmetic substract, Nikunj A Dadhania, 2017/02/22
- [Qemu-devel] [PATCH v3 06/10] target/ppc: update overflow flags for add/sub, Nikunj A Dadhania, 2017/02/22
- [Qemu-devel] [PATCH v3 08/10] target/ppc: add ov32 flag for multiply low insns, Nikunj A Dadhania, 2017/02/22
- [Qemu-devel] [PATCH v3 09/10] target/ppc: add ov32 flag in divide operations, Nikunj A Dadhania, 2017/02/22
- [Qemu-devel] [PATCH v3 07/10] target/ppc: use tcg ops for neg instruction, Nikunj A Dadhania, 2017/02/22
- [Qemu-devel] [PATCH v3 10/10] target/ppc: add mcrxrx instruction, Nikunj A Dadhania, 2017/02/22
- [Qemu-devel] [PATCH v3 02/10] target/ppc: optimize gen_write_xer(), Nikunj A Dadhania, 2017/02/22
- Re: [Qemu-devel] [PATCH v3 00/10] POWER9 TCG enablements - part15,
David Gibson <=