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[Qemu-devel] [PATCH 1/1] s390x/css: handle format-0 TIC CCW correctly
From: |
Cornelia Huck |
Subject: |
[Qemu-devel] [PATCH 1/1] s390x/css: handle format-0 TIC CCW correctly |
Date: |
Thu, 23 Feb 2017 13:08:27 +0100 |
From: Dong Jia Shi <address@hidden>
For TIC CCW, bit positions 8-32 of the format-1 CCW must contain zeros;
otherwise, a program-check condition is generated. For format-0 TIC CCWs,
bits 32-63 are ignored.
To convert TIC from format-0 CCW to format-1 CCW correctly, let's clear
bits 8-32 to guarantee compatibility.
Reviewed-by: Pierre Morel <address@hidden>
Signed-off-by: Dong Jia Shi <address@hidden>
Signed-off-by: Cornelia Huck <address@hidden>
---
hw/s390x/css.c | 15 +++++++++------
1 file changed, 9 insertions(+), 6 deletions(-)
diff --git a/hw/s390x/css.c b/hw/s390x/css.c
index 0f2580d644..e32b2a4d42 100644
--- a/hw/s390x/css.c
+++ b/hw/s390x/css.c
@@ -368,13 +368,16 @@ static CCW1 copy_ccw_from_guest(hwaddr addr, bool fmt1)
ret.cda = be32_to_cpu(tmp1.cda);
} else {
cpu_physical_memory_read(addr, &tmp0, sizeof(tmp0));
- ret.cmd_code = tmp0.cmd_code;
- ret.flags = tmp0.flags;
- ret.count = be16_to_cpu(tmp0.count);
- ret.cda = be16_to_cpu(tmp0.cda1) | (tmp0.cda0 << 16);
- if ((ret.cmd_code & 0x0f) == CCW_CMD_TIC) {
- ret.cmd_code &= 0x0f;
+ if ((tmp0.cmd_code & 0x0f) == CCW_CMD_TIC) {
+ ret.cmd_code = CCW_CMD_TIC;
+ ret.flags = 0;
+ ret.count = 0;
+ } else {
+ ret.cmd_code = tmp0.cmd_code;
+ ret.flags = tmp0.flags;
+ ret.count = be16_to_cpu(tmp0.count);
}
+ ret.cda = be16_to_cpu(tmp0.cda1) | (tmp0.cda0 << 16);
}
return ret;
}
--
2.11.0