[Qemu-devel] [PATCH v4 13/15] target/ppc: update OV/OV32 flags for add/sub

[Nikunj A Dadhania]

* SO and OV reflects overflow of the 64-bit result in 64-bit mode and
  overflow of the low-order 32-bit result in 32-bit mode

* OV32 reflects overflow of the low-order 32-bit independent of the mode

Signed-off-by: Nikunj A Dadhania <address@hidden>
---
 target/ppc/translate.c | 15 ++++++++++++---
 1 file changed, 12 insertions(+), 3 deletions(-)

diff --git a/target/ppc/translate.c b/target/ppc/translate.c
index f7d37b0..dc75cca 100644
--- a/target/ppc/translate.c
+++ b/target/ppc/translate.c
@@ -874,6 +874,7 @@ static inline void gen_op_arith_compute_ov(DisasContext 
*ctx, TCGv arg0,
 {
     TCGv t0 = tcg_temp_new();
     TCGv ov = tcg_temp_new();
+    TCGv ov32 = tcg_temp_new();
 
     tcg_gen_xor_tl(ov, arg0, arg2);
     tcg_gen_xor_tl(t0, arg1, arg2);
@@ -884,11 +885,19 @@ static inline void gen_op_arith_compute_ov(DisasContext 
*ctx, TCGv arg0,
     }
     tcg_temp_free(t0);
     if (NARROW_MODE(ctx)) {
-        tcg_gen_ext32s_tl(ov, ov);
+        tcg_gen_extract_tl(ov, ov, 31, 1);
+        if (is_isa300(ctx)) {
+            tcg_gen_mov_tl(ov32, ov);
+        }
+    } else {
+        if (is_isa300(ctx)) {
+            tcg_gen_extract_tl(ov32, ov, 31, 1);
+        }
+        tcg_gen_extract_tl(ov, ov, 63, 1);
     }
-    tcg_gen_shri_tl(ov, ov, TARGET_LONG_BITS - 1);
-    gen_op_update_ov_legacy(ov);
+    gen_op_update_ov(ctx, ov, ov32);
     tcg_temp_free(ov);
+    tcg_temp_free(ov32);
 }
 
 static inline void gen_op_arith_compute_ca32(DisasContext *ctx, TCGv ca32,
-- 
2.7.4