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Re: [Qemu-devel] [PATCH v4 00/15] POWER9 TCG enablements - part15
From: |
Nikunj A Dadhania |
Subject: |
Re: [Qemu-devel] [PATCH v4 00/15] POWER9 TCG enablements - part15 |
Date: |
Fri, 24 Feb 2017 11:23:51 +0530 |
User-agent: |
Notmuch/0.21 (https://notmuchmail.org) Emacs/25.0.94.1 (x86_64-redhat-linux-gnu) |
David Gibson <address@hidden> writes:
> [ Unknown signature status ]
> On Fri, Feb 24, 2017 at 01:26:25AM +0530, Nikunj A Dadhania wrote:
>> Patches:
>> 01-06 Cleans up the XER split out variables and now the
>> flag bits are stored in XER at their respective places
>>
>> 07-14 Contains implentation of CA32 and OV32 bits added to the
>> ISA 3.0. Various fixed-point arithmetic instructions are
>> updated to take care of the newer flags.
>>
>> 15 Finally the last patch adds new instruction mcrxrx, that helps
>> reading the carry (CA and CA32) and the overflow (OV and OV32) flags
>
> I've applied 1/15, I've rest the left pending correction of 2/15 and
> discussions on the rest.
I thought of changing back to previous implementation, and posted v5 :-)
/me needs to slow down !
Regards,
Nikunj
- [Qemu-devel] [PATCH v4 06/15] target/ppc: remove xer split-out flags(so, ov, ca), (continued)
- [Qemu-devel] [PATCH v4 05/15] target/ppc: add gen_op_update_ov_legacy() helper, Nikunj A Dadhania, 2017/02/23
- [Qemu-devel] [PATCH v4 14/15] target/ppc: use tcg ops for neg instruction, Nikunj A Dadhania, 2017/02/23
- [Qemu-devel] [PATCH v4 09/15] target/ppc: update ca32 in arithmetic substract, Nikunj A Dadhania, 2017/02/23
- [Qemu-devel] [PATCH v4 15/15] target/ppc: add mcrxrx instruction, Nikunj A Dadhania, 2017/02/23
- [Qemu-devel] [PATCH v4 10/15] target/ppc: add gen_op_update_ov_isa300(), Nikunj A Dadhania, 2017/02/23
- Re: [Qemu-devel] [PATCH v4 00/15] POWER9 TCG enablements - part15, David Gibson, 2017/02/24
- Re: [Qemu-devel] [PATCH v4 00/15] POWER9 TCG enablements - part15,
Nikunj A Dadhania <=