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[Qemu-devel] [PULL 08/30] Add missing fp_access_check() to aarch64 crypt
From: |
Peter Maydell |
Subject: |
[Qemu-devel] [PULL 08/30] Add missing fp_access_check() to aarch64 crypto instructions |
Date: |
Mon, 27 Feb 2017 18:04:37 +0000 |
From: Nick Reilly <address@hidden>
The aarch64 crypto instructions for AES and SHA are missing the
check for if the FPU is enabled.
Signed-off-by: Nick Reilly <address@hidden>
Reviewed-by: Peter Maydell <address@hidden>
Signed-off-by: Peter Maydell <address@hidden>
---
target/arm/translate-a64.c | 12 ++++++++++++
1 file changed, 12 insertions(+)
diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c
index e15eae6..24de30d 100644
--- a/target/arm/translate-a64.c
+++ b/target/arm/translate-a64.c
@@ -10933,6 +10933,10 @@ static void disas_crypto_aes(DisasContext *s, uint32_t
insn)
return;
}
+ if (!fp_access_check(s)) {
+ return;
+ }
+
/* Note that we convert the Vx register indexes into the
* index within the vfp.regs[] array, so we can share the
* helper with the AArch32 instructions.
@@ -10997,6 +11001,10 @@ static void disas_crypto_three_reg_sha(DisasContext
*s, uint32_t insn)
return;
}
+ if (!fp_access_check(s)) {
+ return;
+ }
+
tcg_rd_regno = tcg_const_i32(rd << 1);
tcg_rn_regno = tcg_const_i32(rn << 1);
tcg_rm_regno = tcg_const_i32(rm << 1);
@@ -11060,6 +11068,10 @@ static void disas_crypto_two_reg_sha(DisasContext *s,
uint32_t insn)
return;
}
+ if (!fp_access_check(s)) {
+ return;
+ }
+
tcg_rd_regno = tcg_const_i32(rd << 1);
tcg_rn_regno = tcg_const_i32(rn << 1);
--
2.7.4
- [Qemu-devel] [PULL 20/30] armv7m: VECTCLRACTIVE and VECTRESET are UNPREDICTABLE, (continued)
- [Qemu-devel] [PULL 20/30] armv7m: VECTCLRACTIVE and VECTRESET are UNPREDICTABLE, Peter Maydell, 2017/02/27
- [Qemu-devel] [PULL 21/30] armv7m: Extract "exception taken" code into functions, Peter Maydell, 2017/02/27
- [Qemu-devel] [PULL 24/30] armv7m: Allow SHCSR writes to change pending and active bits, Peter Maydell, 2017/02/27
- [Qemu-devel] [PULL 17/30] armv7m: Escalate exceptions to HardFault if necessary, Peter Maydell, 2017/02/27
- [Qemu-devel] [PULL 15/30] armv7m: Fix condition check for taking exceptions, Peter Maydell, 2017/02/27
- [Qemu-devel] [PULL 22/30] armv7m: Check exception return consistency, Peter Maydell, 2017/02/27
- [Qemu-devel] [PULL 26/30] hw/sd: add card-reparenting function, Peter Maydell, 2017/02/27
- [Qemu-devel] [PULL 16/30] arm: gic: Remove references to NVIC, Peter Maydell, 2017/02/27
- [Qemu-devel] [PULL 01/30] target-arm: Implement BCM2835 hardware RNG, Peter Maydell, 2017/02/27
- [Qemu-devel] [PULL 10/30] hw/arm/virt: Add a user option to disallow ITS instantiation, Peter Maydell, 2017/02/27
- [Qemu-devel] [PULL 08/30] Add missing fp_access_check() to aarch64 crypto instructions,
Peter Maydell <=
- [Qemu-devel] [PULL 23/30] armv7m: Raise correct kind of UsageFault for attempts to execute ARM code, Peter Maydell, 2017/02/27
- [Qemu-devel] [PULL 07/30] hw/arm/virt: fix cpu object reference leak, Peter Maydell, 2017/02/27
- [Qemu-devel] [PULL 25/30] bcm2835_sdhost: add bcm2835 sdhost controller, Peter Maydell, 2017/02/27
- [Qemu-devel] [PULL 05/30] sd: sdhci: conditionally invoke multi block transfer, Peter Maydell, 2017/02/27
- [Qemu-devel] [PULL 30/30] hw/arm/exynos: Fix proper mapping of CPUs by providing real cluster ID, Peter Maydell, 2017/02/27
- [Qemu-devel] [PULL 02/30] bcm2835_rng: Use qcrypto_random_bytes() rather than rand(), Peter Maydell, 2017/02/27
- [Qemu-devel] [PULL 06/30] sd: sdhci: Remove block count enable check in single block transfers, Peter Maydell, 2017/02/27
- [Qemu-devel] [PULL 13/30] armv7m: Implement reading and writing of PRIGROUP, Peter Maydell, 2017/02/27
- [Qemu-devel] [PULL 11/30] ARM i.MX timers: fix reset handling, Peter Maydell, 2017/02/27
- [Qemu-devel] [PULL 27/30] bcm2835_gpio: add bcm2835 gpio controller, Peter Maydell, 2017/02/27