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[Qemu-devel] [PULL 09/17] target/ppc/POWER9: Add cpu_has_work function f
From: |
David Gibson |
Subject: |
[Qemu-devel] [PULL 09/17] target/ppc/POWER9: Add cpu_has_work function for POWER9 |
Date: |
Fri, 3 Mar 2017 14:24:59 +1100 |
From: Suraj Jitindar Singh <address@hidden>
The cpu has work function is used to mask interrupts used to determine
if there is work for the cpu based on the LPCR. Add a function to do this
for POWER9 and add it to the POWER9 cpu definition. This is similar to that
for POWER8 except using the LPCR bits as defined for POWER9.
Signed-off-by: Suraj Jitindar Singh <address@hidden>
Reviewed-by: David Gibson <address@hidden>
Signed-off-by: David Gibson <address@hidden>
---
target/ppc/translate_init.c | 45 +++++++++++++++++++++++++++++++++++++++++++++
1 file changed, 45 insertions(+)
diff --git a/target/ppc/translate_init.c b/target/ppc/translate_init.c
index dc2f8eb..c1a9014 100644
--- a/target/ppc/translate_init.c
+++ b/target/ppc/translate_init.c
@@ -8858,10 +8858,54 @@ static bool ppc_pvr_match_power9(PowerPCCPUClass *pcc,
uint32_t pvr)
return false;
}
+static bool cpu_has_work_POWER9(CPUState *cs)
+{
+ PowerPCCPU *cpu = POWERPC_CPU(cs);
+ CPUPPCState *env = &cpu->env;
+
+ if (cs->halted) {
+ if (!(cs->interrupt_request & CPU_INTERRUPT_HARD)) {
+ return false;
+ }
+ /* External Exception */
+ if ((env->pending_interrupts & (1u << PPC_INTERRUPT_EXT)) &&
+ (env->spr[SPR_LPCR] & LPCR_EEE)) {
+ return true;
+ }
+ /* Decrementer Exception */
+ if ((env->pending_interrupts & (1u << PPC_INTERRUPT_DECR)) &&
+ (env->spr[SPR_LPCR] & LPCR_DEE)) {
+ return true;
+ }
+ /* Machine Check or Hypervisor Maintenance Exception */
+ if ((env->pending_interrupts & (1u << PPC_INTERRUPT_MCK |
+ 1u << PPC_INTERRUPT_HMI)) && (env->spr[SPR_LPCR] & LPCR_OEE)) {
+ return true;
+ }
+ /* Privileged Doorbell Exception */
+ if ((env->pending_interrupts & (1u << PPC_INTERRUPT_DOORBELL)) &&
+ (env->spr[SPR_LPCR] & LPCR_PDEE)) {
+ return true;
+ }
+ /* Hypervisor Doorbell Exception */
+ if ((env->pending_interrupts & (1u << PPC_INTERRUPT_HDOORBELL)) &&
+ (env->spr[SPR_LPCR] & LPCR_HDEE)) {
+ return true;
+ }
+ if (env->pending_interrupts & (1u << PPC_INTERRUPT_RESET)) {
+ return true;
+ }
+ return false;
+ } else {
+ return msr_ee && (cs->interrupt_request & CPU_INTERRUPT_HARD);
+ }
+}
+
POWERPC_FAMILY(POWER9)(ObjectClass *oc, void *data)
{
DeviceClass *dc = DEVICE_CLASS(oc);
PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
+ CPUClass *cc = CPU_CLASS(oc);
dc->fw_name = "PowerPC,POWER9";
dc->desc = "POWER9";
@@ -8872,6 +8916,7 @@ POWERPC_FAMILY(POWER9)(ObjectClass *oc, void *data)
PCR_COMPAT_2_05;
pcc->init_proc = init_proc_POWER9;
pcc->check_pow = check_pow_nocheck;
+ cc->has_work = cpu_has_work_POWER9;
pcc->insns_flags = PPC_INSNS_BASE | PPC_ISEL | PPC_STRING | PPC_MFTB |
PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |
PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE |
--
2.9.3
- [Qemu-devel] [PULL 00/17] ppc-for-2.9 queue 20170303, David Gibson, 2017/03/02
- [Qemu-devel] [PULL 01/17] target/ppc: Add POWER9/ISAv3.00 to compat_table, David Gibson, 2017/03/02
- [Qemu-devel] [PULL 10/17] hw/ppc/spapr: Add POWER9 to pseries cpu models, David Gibson, 2017/03/02
- [Qemu-devel] [PULL 11/17] target/ppc: Add Instruction Authority Mask Register Check, David Gibson, 2017/03/02
- [Qemu-devel] [PULL 03/17] powernv: Don't test POWER9 CPU yet, David Gibson, 2017/03/02
- [Qemu-devel] [PULL 08/17] target/ppc/POWER9: Add POWER9 pa-features definition, David Gibson, 2017/03/02
- [Qemu-devel] [PULL 09/17] target/ppc/POWER9: Add cpu_has_work function for POWER9,
David Gibson <=
- [Qemu-devel] [PULL 14/17] target/ppc: Rework hash mmu page fault code and add defines for clarity, David Gibson, 2017/03/02
- [Qemu-devel] [PULL 02/17] exec, kvm, target-ppc: Move getrampagesize() to common code, David Gibson, 2017/03/02
- [Qemu-devel] [PULL 04/17] target/ppc/POWER9: Add POWERPC_MMU_V3 bit, David Gibson, 2017/03/02
- [Qemu-devel] [PULL 07/17] target/ppc/POWER9: Add POWER9 mmu fault handler, David Gibson, 2017/03/02
- [Qemu-devel] [PULL 15/17] spapr_pci: Advertise access to PCIe extended config space, David Gibson, 2017/03/02
- [Qemu-devel] [PULL 06/17] target/ppc: Don't gen an SDR1 on POWER9 and rework register creation, David Gibson, 2017/03/02
- [Qemu-devel] [PULL 05/17] target/ppc: Add patb_entry to sPAPRMachineState, David Gibson, 2017/03/02
- [Qemu-devel] [PULL 13/17] target/ppc: Move no-execute and guarded page checking into new function, David Gibson, 2017/03/02