Re: [Qemu-devel] MTD timeout on bootup

[Alistair Francis]

> -----Original Message-----
> From: James Hanley [mailto:address@hidden
> Sent: Friday, 31 March 2017 8:29 AM
> To: Alistair Francis <address@hidden>; Peter Crosthwaite
> <address@hidden>; qemu-devel <address@hidden>
> Subject: MTD timeout on bootup
>
> When trying to bootup a pristine zync image from the zc702 tarball, it would 
> always
> fail with the MTD detection of the serial flash device type command over the 
> SPI.  I
> believe this section of code may have the logic flipped.  Once I changed it 
> to the
> following, I was able to detect the flash type when booting the pristine 
> image from
> Xilinx.

Hey Jim,

First off, thanks for the patch.

In the future do you mind following the guidelines here:
http://wiki.qemu-project.org/Contribute/SubmitAPatch

If you use git format-patch and git send-email to generate the patch and send 
the result
to the mailing list it is much easier for people to review and apply.

Looking at the Xilinx Zynq-700 TRM (page 1754) I see that the Man_start_com bit
specifies to manually start the transmission of data, so it looks like the 
logic already in
the QEMU model is correct. What issue are you seeing that this fixes? Maybe the 
logic
somewhere else is incorrect.

PS: Sorry about the footer, I had to reply from my corporate email account.

Thanks,

Alistair

> -Jim
>
>
> From baaaacca370c13526fd2b8c7b33c7d9e8a6d7b8d Mon Sep 17 00:00:00 2001
> From: Jim Hanley <address@hidden>
> Date: Thu, 23 Mar 2017 10:29:34 -0400
> Subject: [PATCH] MTD writes from the SPI were never being dequeue...
> Signed-off-by:
>
> ---
>  hw/ssi/xilinx_spips.c | 4 ++--
>  1 file changed, 2 insertions(+), 2 deletions(-)
>
> diff --git a/hw/ssi/xilinx_spips.c b/hw/ssi/xilinx_spips.c
> index da8adfa..a3af1f7 100644
> --- a/hw/ssi/xilinx_spips.c
> +++ b/hw/ssi/xilinx_spips.c
> @@ -482,8 +482,8 @@ static void xilinx_spips_write(void *opaque, hwaddr addr,
>      s->regs[addr] = (s->regs[addr] & ~mask) | (value & mask);
>  no_reg_update:
>      xilinx_spips_update_cs_lines(s);
> -    if ((man_start_com && s->regs[R_CONFIG] & MAN_START_EN) ||
> -            (fifo8_is_empty(&s->tx_fifo) && s->regs[R_CONFIG] & 
> MAN_START_EN)) {
> +    if (!((man_start_com && s->regs[R_CONFIG] & MAN_START_EN) ||
> +            (fifo8_is_empty(&s->tx_fifo) && s->regs[R_CONFIG] & 
> MAN_START_EN))) {
>          xilinx_spips_flush_txfifo(s);
>      }
>      xilinx_spips_update_cs_lines(s);
> --
> 2.7.4



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