[Date Prev][Date Next][Thread Prev][Thread Next][Date Index][Thread Index]
[Qemu-devel] [PATCH 0/2] targets/openrisc: Improve exception vectoring.
From: |
Tim 'mithro' Ansell |
Subject: |
[Qemu-devel] [PATCH 0/2] targets/openrisc: Improve exception vectoring. |
Date: |
Tue, 18 Apr 2017 16:15:49 +1000 |
Hi,
This patch series improves the exception vectoring on the OpenRISC platform by
adding support for both the EVBAR register and EPH bit.
This is my first patch to upstream QEMU, so please do point of if I have done
anything silly.
Tim 'mithro' Ansell (2):
target/openrisc: Implement EVBAR register
target/openrisc: Implement EPH bit
target/openrisc/cpu.c | 2 ++
target/openrisc/cpu.h | 7 +++++++
target/openrisc/interrupt.c | 9 ++++++++-
target/openrisc/sys_helper.c | 7 +++++++
4 files changed, 24 insertions(+), 1 deletion(-)
--
2.12.1