[Date Prev][Date Next][Thread Prev][Thread Next][Date Index][Thread Index]
[Qemu-devel] [PULL 17/24] arm: Thumb shift operations should not permit
From: |
Peter Maydell |
Subject: |
[Qemu-devel] [PULL 17/24] arm: Thumb shift operations should not permit interworking branches |
Date: |
Thu, 20 Apr 2017 17:41:03 +0100 |
In Thumb mode, the only instructions which can cause an interworking
branch by writing the PC are BLX, BX, BXJ, LDR, POP and LDM. Unlike
ARM mode, data processing instructions which target the PC do not
cause interworking branches.
When we added support for doing interworking branches on writes to
PC from data processing instructions in commit 21aeb3430ce7ba, we
accidentally changed a Thumb instruction to have interworking
branch behaviour for writes to PC. (MOV, MOVS register-shifted
register, encoding T2; this is the standard encoding for
LSL/LSR/ASR/ROR (register).)
For this encoding, behaviour with Rd == R15 is specified as
UNPREDICTABLE, so allowing an interworking branch is within
spec, but it's confusing and differs from our handling of this
class of UNPREDICTABLE for other Thumb ALU operations. Make
it perform a simple (non-interworking) branch like the others.
Signed-off-by: Peter Maydell <address@hidden>
Reviewed-by: Richard Henderson <address@hidden>
Reviewed-by: Philippe Mathieu-Daudé <address@hidden>
Message-id: address@hidden
---
target/arm/translate.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/target/arm/translate.c b/target/arm/translate.c
index fe3f442..ddc62b6 100644
--- a/target/arm/translate.c
+++ b/target/arm/translate.c
@@ -9959,7 +9959,7 @@ static int disas_thumb2_insn(CPUARMState *env,
DisasContext *s, uint16_t insn_hw
gen_arm_shift_reg(tmp, op, tmp2, logic_cc);
if (logic_cc)
gen_logic_CC(tmp);
- store_reg_bx(s, rd, tmp);
+ store_reg(s, rd, tmp);
break;
case 1: /* Sign/zero extend. */
op = (insn >> 20) & 7;
--
2.7.4
- [Qemu-devel] [PULL 00/24] target-arm queue, Peter Maydell, 2017/04/20
- [Qemu-devel] [PULL 16/24] arm: Don't implement BXJ on M-profile CPUs, Peter Maydell, 2017/04/20
- [Qemu-devel] [PULL 17/24] arm: Thumb shift operations should not permit interworking branches,
Peter Maydell <=
- [Qemu-devel] [PULL 18/24] arm: Factor out "generate right kind of step exception", Peter Maydell, 2017/04/20
- [Qemu-devel] [PULL 15/24] xlnx-zynqmp: Set the Cadence GEM revision, Peter Maydell, 2017/04/20
- [Qemu-devel] [PULL 12/24] cadence_gem: Correct the multi-queue can rx logic, Peter Maydell, 2017/04/20
- [Qemu-devel] [PULL 19/24] arm: Move gen_set_condexec() and gen_set_pc_im() up in the file, Peter Maydell, 2017/04/20
- [Qemu-devel] [PULL 14/24] cadence_gem: Make the revision a property, Peter Maydell, 2017/04/20
- [Qemu-devel] [PULL 20/24] arm: Move condition-failed codepath generation out of if(), Peter Maydell, 2017/04/20
- [Qemu-devel] [PULL 11/24] cadence_gem: Read the correct queue descriptor, Peter Maydell, 2017/04/20
- [Qemu-devel] [PULL 09/24] arm/kvm: Remove trailing newlines from error_report(), Peter Maydell, 2017/04/20
- [Qemu-devel] [PULL 03/24] hw/char/exynos4210_uart: Constify static array and few arguments, Peter Maydell, 2017/04/20
- [Qemu-devel] [PULL 08/24] stellaris: Don't hw_error() on bad register accesses, Peter Maydell, 2017/04/20