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[Qemu-devel] [PULL 18/24] arm: Factor out "generate right kind of step e
From: |
Peter Maydell |
Subject: |
[Qemu-devel] [PULL 18/24] arm: Factor out "generate right kind of step exception" |
Date: |
Thu, 20 Apr 2017 17:41:04 +0100 |
We currently have two places that do:
if (dc->ss_active) {
gen_step_complete_exception(dc);
} else {
gen_exception_internal(EXCP_DEBUG);
}
Factor this out into its own function, as we're about to add
a third place that needs the same logic.
Signed-off-by: Peter Maydell <address@hidden>
Reviewed-by: Philippe Mathieu-Daudé <address@hidden>
Reviewed-by: Richard Henderson <address@hidden>
Message-id: address@hidden
---
target/arm/translate.c | 28 ++++++++++++++++------------
1 file changed, 16 insertions(+), 12 deletions(-)
diff --git a/target/arm/translate.c b/target/arm/translate.c
index ddc62b6..870e320 100644
--- a/target/arm/translate.c
+++ b/target/arm/translate.c
@@ -296,6 +296,19 @@ static void gen_step_complete_exception(DisasContext *s)
s->is_jmp = DISAS_EXC;
}
+static void gen_singlestep_exception(DisasContext *s)
+{
+ /* Generate the right kind of exception for singlestep, which is
+ * either the architectural singlestep or EXCP_DEBUG for QEMU's
+ * gdb singlestepping.
+ */
+ if (s->ss_active) {
+ gen_step_complete_exception(s);
+ } else {
+ gen_exception_internal(EXCP_DEBUG);
+ }
+}
+
static void gen_smul_dual(TCGv_i32 a, TCGv_i32 b)
{
TCGv_i32 tmp1 = tcg_temp_new_i32();
@@ -11998,24 +12011,15 @@ void gen_intermediate_code(CPUARMState *env,
TranslationBlock *tb)
gen_set_pc_im(dc, dc->pc);
/* fall through */
default:
- if (dc->ss_active) {
- gen_step_complete_exception(dc);
- } else {
- /* FIXME: Single stepping a WFI insn will not halt
- the CPU. */
- gen_exception_internal(EXCP_DEBUG);
- }
+ /* FIXME: Single stepping a WFI insn will not halt the CPU. */
+ gen_singlestep_exception(dc);
}
if (dc->condjmp) {
/* "Condition failed" instruction codepath. */
gen_set_label(dc->condlabel);
gen_set_condexec(dc);
gen_set_pc_im(dc, dc->pc);
- if (dc->ss_active) {
- gen_step_complete_exception(dc);
- } else {
- gen_exception_internal(EXCP_DEBUG);
- }
+ gen_singlestep_exception(dc);
}
} else {
/* While branches must always occur at the end of an IT block,
--
2.7.4
- [Qemu-devel] [PULL 00/24] target-arm queue, Peter Maydell, 2017/04/20
- [Qemu-devel] [PULL 16/24] arm: Don't implement BXJ on M-profile CPUs, Peter Maydell, 2017/04/20
- [Qemu-devel] [PULL 17/24] arm: Thumb shift operations should not permit interworking branches, Peter Maydell, 2017/04/20
- [Qemu-devel] [PULL 18/24] arm: Factor out "generate right kind of step exception",
Peter Maydell <=
- [Qemu-devel] [PULL 15/24] xlnx-zynqmp: Set the Cadence GEM revision, Peter Maydell, 2017/04/20
- [Qemu-devel] [PULL 12/24] cadence_gem: Correct the multi-queue can rx logic, Peter Maydell, 2017/04/20
- [Qemu-devel] [PULL 19/24] arm: Move gen_set_condexec() and gen_set_pc_im() up in the file, Peter Maydell, 2017/04/20
- [Qemu-devel] [PULL 14/24] cadence_gem: Make the revision a property, Peter Maydell, 2017/04/20
- [Qemu-devel] [PULL 20/24] arm: Move condition-failed codepath generation out of if(), Peter Maydell, 2017/04/20
- [Qemu-devel] [PULL 11/24] cadence_gem: Read the correct queue descriptor, Peter Maydell, 2017/04/20
- [Qemu-devel] [PULL 09/24] arm/kvm: Remove trailing newlines from error_report(), Peter Maydell, 2017/04/20
- [Qemu-devel] [PULL 03/24] hw/char/exynos4210_uart: Constify static array and few arguments, Peter Maydell, 2017/04/20
- [Qemu-devel] [PULL 08/24] stellaris: Don't hw_error() on bad register accesses, Peter Maydell, 2017/04/20
- [Qemu-devel] [PULL 05/24] target/arm: Add missing entries to excnames[] for log strings, Peter Maydell, 2017/04/20